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i82801gx: Fix port status in AHCI mode
[coreboot.git]
/
src
/
southbridge
/
intel
/
i82801gx
/
sata.c
diff --git
a/src/southbridge/intel/i82801gx/sata.c
b/src/southbridge/intel/i82801gx/sata.c
index c3908489ebab312a02ebfe338e1f69f68740104a..0e7a1a740c9df1c2694f8c74243c62dff75ed61c 100644
(file)
--- a/
src/southbridge/intel/i82801gx/sata.c
+++ b/
src/southbridge/intel/i82801gx/sata.c
@@
-30,6
+30,8
@@
static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
{
u32 reg32;
u16 reg16;
+ u32 *ahci_bar;
+
/* Get the chip configuration */
config_t *config = dev->chip_info;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@
-106,9
+108,14
@@
static void sata_init(struct device *dev)
/* Set Sata Controller Mode. */
pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
/* Set Sata Controller Mode. */
pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
- /* Port 0 & 1 enable */
+ /* In ACHI mode, bit[3:0] must always be set
+ * (Port status is controlled through AHCI BAR)
+ */
pci_write_config8(dev, 0x92, 0x0f);
pci_write_config8(dev, 0x92, 0x0f);
+ ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
+ ahci_bar[3] = config->sata_ports_implemented;
+
/* SATA Initialization register */
pci_write_config32(dev, 0x94, 0x1a000180);
} else {
/* SATA Initialization register */
pci_write_config32(dev, 0x94, 0x1a000180);
} else {