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Convert some comments to proper Doxygen syntax.
[coreboot.git]
/
src
/
southbridge
/
intel
/
i82801cx
/
i82801cx.h
diff --git
a/src/southbridge/intel/i82801cx/i82801cx.h
b/src/southbridge/intel/i82801cx/i82801cx.h
index e0d377a9cdc75cc7d1de3f567f029c72aebdd753..da518a3660ad5ee6b4eeb13ca55b732fba5ab5c4 100644
(file)
--- a/
src/southbridge/intel/i82801cx/i82801cx.h
+++ b/
src/southbridge/intel/i82801cx/i82801cx.h
@@
-32,9
+32,7
@@
void i82801cx_hard_reset(void);
#define RTC_POWER_FAILED (1<<1)
#define SLEEP_AFTER_POWER_FAIL (1<<0)
#define RTC_POWER_FAILED (1<<1)
#define SLEEP_AFTER_POWER_FAIL (1<<0)
-/********************************************************************/
-/* IDE Controller */
-/********************************************************************/
+/* IDE controller: */
// PCI Configuration Space (D31:F1)
#define IDE_TIM_PRI 0x40 // IDE timings, primary
// PCI Configuration Space (D31:F1)
#define IDE_TIM_PRI 0x40 // IDE timings, primary
@@
-44,9
+42,7
@@
void i82801cx_hard_reset(void);
// IDE_TIM bits
#define IDE_DECODE_ENABLE (1<<15)
// IDE_TIM bits
#define IDE_DECODE_ENABLE (1<<15)
-/********************************************************************/
-/* SMBus */
-/********************************************************************/
+/* SMBus: */
// PCI Configuration Space (D31:F3)
#define SMB_BASE 0x20
// PCI Configuration Space (D31:F3)
#define SMB_BASE 0x20