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remove trailing whitespace
[coreboot.git]
/
src
/
southbridge
/
amd
/
sr5650
/
sr5650.c
diff --git
a/src/southbridge/amd/sr5650/sr5650.c
b/src/southbridge/amd/sr5650/sr5650.c
index 616ca44ee6d458f6f3ffe3dd73da3298400c2e3e..14b919de724298a0d9aad30731ee997cb3ba6ae4 100644
(file)
--- a/
src/southbridge/amd/sr5650/sr5650.c
+++ b/
src/southbridge/amd/sr5650/sr5650.c
@@
-266,15
+266,21
@@
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
}
/*
}
/*
-* Compliant with CIM_33's ATINB_SetToms.
-* Set Top Of Memory below and above 4G.
-*/
+ * Set Top Of Memory below and above 4G.
+ */
void sr5650_set_tom(device_t nb_dev)
{
void sr5650_set_tom(device_t nb_dev)
{
- extern u64 uma_memory_base;
+ msr_t sysmem;
+
+ /* The system top memory in SR56X0. */
+ sysmem = rdmsr(0xc001001A);
+ printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
+ pci_write_config32(nb_dev, 0x90, sysmem.lo);
- /* set TOM */
- pci_write_config32(nb_dev, 0x90, uma_memory_base);
+ sysmem = rdmsr(0xc001001D);
+ printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
+ htiu_write_index(nb_dev, 0x31, sysmem.hi);
+ htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
}
u32 get_vid_did(device_t dev)
}
u32 get_vid_did(device_t dev)
@@
-308,7
+314,7
@@
void sr5650_nb_pci_table(device_t nb_dev)
temp8 &= ~(1<<1);
pci_write_config8(nb_dev, 0x8d, temp8);
temp8 &= ~(1<<1);
pci_write_config8(nb_dev, 0x8d, temp8);
- /*
set temporary NB TOM to 0x4000000
0. */
+ /*
The system top memory in SR56X
0. */
sr5650_set_tom(nb_dev);
/* Program NB HTIU table. */
sr5650_set_tom(nb_dev);
/* Program NB HTIU table. */
@@
-424,6
+430,11
@@
void sr5650_enable(device_t dev)
default:
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
}
default:
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
}
+
+ /* Lock HWInit Register after the last device was done */
+ if (dev_ind == 13) {
+ sr56x0_lock_hwinitreg();
+ }
}
struct chip_operations southbridge_amd_sr5650_ops = {
}
struct chip_operations southbridge_amd_sr5650_ops = {