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There was a programming error which made most USB port4 setup wrong. This patch uses...
[coreboot.git]
/
src
/
southbridge
/
amd
/
cs5536
/
cs5536.c
diff --git
a/src/southbridge/amd/cs5536/cs5536.c
b/src/southbridge/amd/cs5536/cs5536.c
index 3f947cf17a9f61cab7f195df14d105e580a96df0..51e9c6f788756d904150b57072d452b20a379511 100644
(file)
--- a/
src/southbridge/amd/cs5536/cs5536.c
+++ b/
src/southbridge/amd/cs5536/cs5536.c
@@
-1,5
+1,5
@@
/*
/*
- * This file is part of the
LinuxBIOS
project.
+ * This file is part of the
coreboot
project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
@@
-409,7
+409,7
@@
static void uarts_init(struct southbridge_amd_cs5536_config *sb)
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
{
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
{
- uint
32
_t *bar;
+ uint
8
_t *bar;
msr_t msr;
device_t dev;
msr_t msr;
device_t dev;
@@
-425,32
+425,33
@@
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
/* write to clear diag register */
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
/* write to clear diag register */
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
- bar = (uint
32
_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (uint
8
_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writeable */
/* Make HCCPARAMS writeable */
-
*(bar + IPREG04) |= USB_HCCPW_SET
;
+
writel(readl(bar + IPREG04) | USB_HCCPW_SET, bar + IPREG04)
;
/* ; EECP=50h, IST=01h, ASPC=1 */
/* ; EECP=50h, IST=01h, ASPC=1 */
-
*(bar + HCCPARAMS) = 0x00005012
;
+
writel(0x00005012, bar + HCCPARAMS)
;
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = (uint
32
_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (uint
8
_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-
*(bar + UOCMUX) &= PUEN_SET
;
+
writel(readl(bar + UOCMUX) & PUEN_SET, bar + UOCMUX)
;
/* Host or Device? */
if (sb->enable_USBP4_device) {
/* Host or Device? */
if (sb->enable_USBP4_device) {
-
*(bar + UOCMUX) |= PMUX_DEVICE
;
+
writel(readl(bar + UOCMUX) | PMUX_DEVICE, bar + UOCMUX)
;
} else {
} else {
-
*(bar + UOCMUX) |= PMUX_HOST
;
+
writel(readl(bar + UOCMUX) | PMUX_HOST, bar + UOCMUX)
;
}
/* Overcurrent configuration */
if (sb->enable_USBP4_overcurrent) {
}
/* Overcurrent configuration */
if (sb->enable_USBP4_overcurrent) {
- *(bar + UOCCAP) |= sb->enable_USBP4_overcurrent;
+ writel(readl(bar + UOCCAP)
+ | sb->enable_USBP4_overcurrent, bar + UOCCAP);
}
}
}
}
@@
-464,19
+465,20
@@
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
- bar = (uint
32
_t *) pci_read_config32(dev,
+ bar = (uint
8
_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0);
- *(bar + UDCDEVCTL) |= UDC_SD_SET;
+ writel(readl(bar + UDCDEVCTL) | UDC_SD_SET,
+ bar + UDCDEVCTL);
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = (uint
32
_t *) pci_read_config32(dev,
+ bar = (uint
8
_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0);
-
*(bar + UOCCTL) |= PADEN_SET
;
-
*(bar + UOCCAP) |= APU_SET
;
+
writel(readl(bar + UOCCTL) | PADEN_SET, bar + UOCCTL)
;
+
writel(readl(bar + UOCCAP) | APU_SET, bar + UOCCAP)
;
}
}
}
}
@@
-511,7
+513,7
@@
void chipsetinit(void)
post_code(P80_CHIPSET_INIT);
post_code(P80_CHIPSET_INIT);
- /* we hope NEVER to be in
linuxbios
when S3 resumes
+ /* we hope NEVER to be in
coreboot
when S3 resumes
if (! IsS3Resume()) */
{
struct acpiinit *aci = acpi_init_table;
if (! IsS3Resume()) */
{
struct acpiinit *aci = acpi_init_table;