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[seabios.git]
/
src
/
smm.c
diff --git
a/src/smm.c
b/src/smm.c
index 9db02d7154cf7fd539ccfdf23f48f2fcf9ca0755..72e5e88c554b1603d67d1a8c332a5269f13aeaf4 100644
(file)
--- a/
src/smm.c
+++ b/
src/smm.c
@@
-110,30
+110,30
@@
smm_relocate_and_restore(void)
#define PIIX_APMC_EN (1 << 25)
// This code is hardcoded for PIIX4 Power Management device.
#define PIIX_APMC_EN (1 << 25)
// This code is hardcoded for PIIX4 Power Management device.
-static void piix4_apmc_smm_init(
u16 bdf
, void *arg)
+static void piix4_apmc_smm_init(
struct pci_device *pci
, void *arg)
{
{
-
int i440_bdf
= pci_find_device(PCI_VENDOR_ID_INTEL
- , PCI_DEVICE_ID_INTEL_82441);
- if (
i440_bdf < 0
)
+
struct pci_device *i440_pci
= pci_find_device(PCI_VENDOR_ID_INTEL
+
, PCI_DEVICE_ID_INTEL_82441);
+ if (
!i440_pci
)
return;
/* check if SMM init is already done */
return;
/* check if SMM init is already done */
- u32 value = pci_config_readl(bdf, PIIX_DEVACTB);
+ u32 value = pci_config_readl(
pci->
bdf, PIIX_DEVACTB);
if (value & PIIX_APMC_EN)
return;
/* enable the SMM memory window */
if (value & PIIX_APMC_EN)
return;
/* enable the SMM memory window */
- pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x48);
+ pci_config_writeb(i440_
pci->
bdf, I440FX_SMRAM, 0x02 | 0x48);
smm_save_and_copy();
/* enable SMI generation when writing to the APMC register */
smm_save_and_copy();
/* enable SMI generation when writing to the APMC register */
- pci_config_writel(bdf, PIIX_DEVACTB, value | PIIX_APMC_EN);
+ pci_config_writel(
pci->
bdf, PIIX_DEVACTB, value | PIIX_APMC_EN);
smm_relocate_and_restore();
/* close the SMM memory window and enable normal SMM */
smm_relocate_and_restore();
/* close the SMM memory window and enable normal SMM */
- pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x08);
+ pci_config_writeb(i440_
pci->
bdf, I440FX_SMRAM, 0x02 | 0x08);
}
static const struct pci_device_id smm_init_tbl[] = {
}
static const struct pci_device_id smm_init_tbl[] = {