+ // Propagate required bus resources to parent busses.
+ int secondary_bus;
+ for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
+ struct pci_bus *s = &busses[secondary_bus];
+ if (!s->bus_dev)
+ continue;
+ struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
+ int type;
+ for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
+ u32 limit = (type == PCI_REGION_TYPE_IO) ?
+ PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
+ s->r[type].size = s->r[type].sum;
+ if (s->r[type].size < limit)
+ s->r[type].size = limit;
+ s->r[type].size = pci_size_roundup(s->r[type].size);
+ pci_bios_bus_reserve(parent, type, s->r[type].size);
+ }
+ dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
+ secondary_bus,
+ s->r[PCI_REGION_TYPE_IO].size,
+ s->r[PCI_REGION_TYPE_MEM].size,
+ s->r[PCI_REGION_TYPE_PREFMEM].size);
+ }
+}
+
+#define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1)
+
+// Setup region bases (given the regions' size and alignment)
+static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end)
+{
+ bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
+
+ int reg1 = PCI_REGION_TYPE_PREFMEM, reg2 = PCI_REGION_TYPE_MEM;
+ if (bus->r[reg1].sum < bus->r[reg2].sum) {
+ // Swap regions so larger area is more likely to align well.
+ reg1 = PCI_REGION_TYPE_MEM;
+ reg2 = PCI_REGION_TYPE_PREFMEM;
+ }
+ bus->r[reg2].base = ROOT_BASE(end, bus->r[reg2].sum, bus->r[reg2].max);
+ bus->r[reg1].base = ROOT_BASE(bus->r[reg2].base, bus->r[reg1].sum
+ , bus->r[reg1].max);
+ if (bus->r[reg1].base < start)
+ // Memory range requested is larger than available.
+ return -1;
+ return 0;
+}
+
+
+/****************************************************************
+ * BAR assignment
+ ****************************************************************/
+
+static void pci_bios_init_bus_bases(struct pci_bus *bus)
+{
+ u32 base, newbase, size;
+ int type, i;
+
+ for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
+ dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
+ bus->r[type].max, bus->r[type].sum, bus->r[type].base);
+ base = bus->r[type].base;
+ for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
+ size = pci_index_to_size(i, type);
+ if (!bus->r[type].count[i])
+ continue;
+ newbase = base + size * bus->r[type].count[i];
+ dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
+ size, bus->r[type].count[i], base, newbase - 1);
+ bus->r[type].bases[i] = base;
+ base = newbase;
+ }
+ }
+}
+
+static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
+{
+ u32 index, addr;
+
+ index = pci_size_to_index(size, type);
+ addr = bus->r[type].bases[index];
+ bus->r[type].bases[index] += pci_index_to_size(index, type);
+ return addr;
+}
+
+#define PCI_IO_SHIFT 8
+#define PCI_MEMORY_SHIFT 16
+#define PCI_PREF_MEMORY_SHIFT 16
+
+static void pci_bios_map_devices(struct pci_bus *busses)
+{
+ // Setup bases for root bus.
+ dprintf(1, "PCI: init bases bus 0 (primary)\n");
+ pci_bios_init_bus_bases(&busses[0]);
+
+ // Map regions on each secondary bus.
+ int secondary_bus;
+ for (secondary_bus=1; secondary_bus<=MaxPCIBus; secondary_bus++) {
+ struct pci_bus *s = &busses[secondary_bus];
+ if (!s->bus_dev)
+ continue;
+ u16 bdf = s->bus_dev->bdf;
+ struct pci_bus *parent = &busses[pci_bdf_to_bus(bdf)];
+ int type;
+ for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
+ s->r[type].base = pci_bios_bus_get_addr(
+ parent, type, s->r[type].size);
+ }
+ dprintf(1, "PCI: init bases bus %d (secondary)\n", secondary_bus);
+ pci_bios_init_bus_bases(s);
+
+ u32 base = s->r[PCI_REGION_TYPE_IO].base;
+ u32 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
+ pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
+ pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
+ pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
+ pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
+
+ base = s->r[PCI_REGION_TYPE_MEM].base;
+ limit = base + s->r[PCI_REGION_TYPE_MEM].size - 1;
+ pci_config_writew(bdf, PCI_MEMORY_BASE, base >> PCI_MEMORY_SHIFT);
+ pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
+
+ base = s->r[PCI_REGION_TYPE_PREFMEM].base;
+ limit = base + s->r[PCI_REGION_TYPE_PREFMEM].size - 1;
+ pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base >> PCI_PREF_MEMORY_SHIFT);
+ pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
+ pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
+ pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);