--- sync_pc : process ()
--- begin
--- end process sync_pc;
---
--- next_state_pc : process ()
--- begin
--- end process next_state_pc;
---
--- output_pc : process ()
--- begin
--- end process output_pc;
+ case state is
+ when IDLE =>
+ null;
+ when FETCH =>
+ get_next <= '1';
+ when FORWARD =>
+ tx_data_i_next <= pc_char;
+ new_i_next <= '1';
+ -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
+ get_next <= '1';
+ when WAIT_UART =>
+ new_i_next <= '1';
+ get_next <= '1';
+ when UART_DONE => null;
+ -- get_next <= '0';
+ -- new_i_next <= '0';
+ when CALC_VAL =>
+ spalte_next <= spalte + 1;
+ if spalte = HSPALTE_MAX + 1 then
+ tx_data_i_next <= x"0a";
+ new_i_next <= '1';
+
+ spalte_next <= 1;
+ zeile_next <= zeile + 1;
+ if zeile = HZEILE_MAX-1 then
+ zeile_next <= 0;
+ end if;
+ end if;
+ end case;
+ end process output_pc;
+
+ next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
+ tx_data_i ,tx_done_i, zeile, pc_char)
+ begin
+ state_next <= state;
+ case state is
+ when IDLE =>
+-- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+ if (rx_new = '1') or btn_a = '0' then
+ state_next <= FETCH;
+ end if;
+ when FETCH =>
+ if pc_done = '1' and tx_done_i = '0' then
+ if pc_char = x"00" then
+ state_next <= UART_DONE;
+ else
+ state_next <= FORWARD;
+ end if;
+ end if;
+ when FORWARD =>
+ state_next <= WAIT_UART;
+ when WAIT_UART =>
+ if (tx_done_i = '1') then
+ state_next <= UART_DONE;
+ end if;
+ when UART_DONE =>
+ state_next <= CALC_VAL;
+ when CALC_VAL =>
+ if spalte = HSPALTE_MAX + 1 and zeile = HZEILE_MAX - 1 then
+ state_next <= IDLE;
+ else
+ state_next <= FETCH;
+ end if;
+ end case;
+ end process next_state_pc;