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removed unresolvedness of some signals and multiple sources
[hwmod.git]
/
src
/
pc_communication.vhd
diff --git
a/src/pc_communication.vhd
b/src/pc_communication.vhd
index 535178496cf1477daedc69e31b7c7d0330d18ac5..4bc09d4c9bd319f745f6a40bd5e9df4071099a93 100644
(file)
--- a/
src/pc_communication.vhd
+++ b/
src/pc_communication.vhd
@@
-32,9
+32,13
@@
end entity pc_communication;
architecture beh of pc_communication is
signal push_history, push_history_next : std_logic;
architecture beh of pc_communication is
signal push_history, push_history_next : std_logic;
- signal spalte, spalte_next :
hspalte
;
- signal zeile , zeile_next :
hzeile
;
+ signal spalte, spalte_next :
integer range 0 to 71
;
+ signal zeile , zeile_next :
integer range 0 to 71
;
signal spalte_up, spalte_up_next : std_logic;
signal spalte_up, spalte_up_next : std_logic;
+ signal get, get_next : std_logic;
+ signal new_i, new_i_next : std_logic;
+ signal tx_done_i, tx_done_i_next : std_logic;
+ signal d_done_i, d_done_i_next : std_logic;
signal char, char_next : hbyte;
signal char_en : std_logic;
signal char, char_next : hbyte;
signal char_en : std_logic;
@@
-43,40
+47,53
@@
architecture beh of pc_communication is
begin
begin
+
+ d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+ d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+ d_get <= get;
+ char_next <= d_char;
+ tx_new <= new_i;
+ d_done_i <= d_done;
+ tx_done_i <= tx_done;
+
sync: process (sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
state <= IDLE;
push_history <= '0';
sync: process (sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
state <= IDLE;
push_history <= '0';
- spalte <= "0000000";
- zeile <= "0000000";
+ spalte <= 0;
+ zeile <= 0;
+ get <= '0';
+ new_i <= '0';
+ tx_data <= "00000000";
+ spalte_up <= '0';
elsif rising_edge(sys_clk) then
push_history <= push_history_next;
spalte <= spalte_next;
zeile <= zeile_next;
state <= state_next;
elsif rising_edge(sys_clk) then
push_history <= push_history_next;
spalte <= spalte_next;
zeile <= zeile_next;
state <= state_next;
+ get <= get_next;
+ new_i <= new_i_next;
+ spalte_up <= spalte_up_next;
if (char_en = '1') then
if (char_en = '1') then
-
state <= state
_next;
+
char <= char
_next;
end if;
end if;
end process sync;
end if;
end if;
end process sync;
- process (spalte_up)
- variable spalte_tmp, zeile_tmp : integer;
+ process (spalte_up, spalte, zeile)
begin
if (spalte_up = '1') then
begin
if (spalte_up = '1') then
- if (spalte > X"45") then
- spalte_next <= "0000000";
- zeile_tmp := to_integer(unsigned(zeile));
- zeile_tmp := zeile_tmp + 1;
- zeile_next <= hbyte(to_unsigned(zeile_tmp,8));
+ if (spalte > 71) then
+ spalte_next <= 0;
+ zeile_next <= zeile + 1;
else
else
- spalte_tmp := to_integer(unsigned(spalte));
- spalte_tmp := spalte_tmp + 1;
- spalte_next <= hbyte(to_unsigned(spalte_tmp,8));
+ spalte_next <= spalte + 1;
zeile_next <= zeile;
end if;
zeile_next <= zeile;
end if;
- spalte_up <= '0';
+ else
+ spalte_next <= spalte;
+ zeile_next <= zeile;
end if;
end process;
end if;
end process;
@@
-95,36
+112,36
@@
begin
end if;
end process async_push_history;
end if;
end process async_push_history;
- output_pc : process (
zeile, spalte
)
+ output_pc : process (
state, zeile, spalte, char
)
begin
begin
- case state is
+ get_next <= '0';
+ new_i_next <= '0';
+ spalte_up_next <= '0';
+ case state is
when IDLE =>
when IDLE =>
- spalte_next <= "0000000";
- zeile_next <= "0000000";
+ null;
when FETCH =>
when FETCH =>
- d_zeile <= zeile;
- d_spalte <= spalte;
- d_get <= '1';
+ get_next <= '1';
char_en <= '1';
char_en <= '1';
- -- wait for timer overflow
- -- increment counter
when FORWARD =>
char_en <= '0';
tx_data <= char;
when FORWARD =>
char_en <= '0';
tx_data <= char;
- tx_new <= '1';
+ new_i_next <= '1';
+ if (tx_done = '1') then
+ spalte_up_next <= '1';
+ end if;
when DONE =>
null;
when DONE =>
null;
- -- be there for a single cycle and then
end case;
end process output_pc;
end case;
end process output_pc;
- next_state_pc : process (rx_new, btn_a)
+ next_state_pc : process (rx_new, btn_a
, d_done, tx_done
)
begin
case state is
when IDLE =>
begin
case state is
when IDLE =>
- if rx_new= '1' or btn_a = '1' then
+ if rx_new
= '1' or btn_a = '1' then
state_next <= FETCH;
state_next <= FETCH;
- char <= d_char; --latch
+
end if;
when FETCH =>
if (d_done = '1') then
end if;
when FETCH =>
if (d_done = '1') then
@@
-135,7
+152,6
@@
begin
state_next <= FETCH;
end if;
when DONE =>
state_next <= FETCH;
end if;
when DONE =>
- -- be there for a single cycle and then
state_next <= IDLE;
end case;
end process next_state_pc;
state_next <= IDLE;
end case;
end process next_state_pc;