-
- */
-#if 0
- static const unsigned int index_register_values[] = {
- /* Output Driver Compensation Control Register
- * Index: 0x00
- * [ 1: 0] CkeDrvStren (CKE Drive Strength)
- * 00 = 1.0x
- * 01 = 1.25x
- * 10 = 1.5x (Default)
- * 11 = 2.0x
- * [ 3: 2] reserved
- * [ 5: 4] CsOdtDrvStren (CS/ODT Drive Strength)
- * 00 = 1.0x
- * 01 = 1.25x
- * 10 = 1.5x (Default)
- * 11 = 2.0x
- * [ 7: 6] reserved
- * [ 9: 8] AddrCmdDrvStren (Address/Command Drive Strength)
- * 00 = 1.0x
- * 01 = 1.25x
- * 10 = 1.5x (Default)
- * 11 = 2.0x
- * [11:10] reserved
- * [13:12] ClkDrvStren (MEMCLK Drive Strength)
- * 00 = 0.75x
- * 01 = 1.0x Default)
- * 10 = 1.25x
- * 11 = 1.5x
- * [15:14] reserved
- * [17:16] DataDrvStren (Data Drive Strength)
- * 00 = 0.75x
- * 01 = 1.0x Default)
- * 10 = 1.25x
- * 11 = 1.5x
- * [19:18] reserved
- * [21:20] DqsDrvStren (DQS Drive Strength)
- * 00 = 0.75x
- * 01 = 1.0x Default)
- * 10 = 1.25x
- * 11 = 1.5x
- * [27:22] reserved
- * [29:28] ProcOdt ( Processor On-die Termination)
- * 00 = 300 ohms +/- 20%
- * 01 = 150 ohms +/- 20%
- * 10 = 75 ohms +/- 20%
- * 11 = reserved
- * [31:30] reserved
- */
- 0x00, 0xcfcccccc, 0x00000000,
- 0x20, 0xcfcccccc, 0x00000000,
- /* Write Data Timing Low Control Register
- * Index 0x01
- * [ 5: 0] WrDatTimeByte0 (Write Data Byte 0 Timing Control)
- * 000000 = no delay
- * 000001 = 1/96 MEMCLK delay
- * 000010 = 2/96 MEMCLK delay
- * ...
- * 101111 = 47/96 MEMCLK delay
- * 11xxxx = reserved
- * [ 7: 6] reserved
- * [13: 8] WrDatTimeByte1 (Write Data Byte 1 Timing Control)
- * [15:14] reserved
- * [21:16] WrDatTimeByte2 (Write Data Byte 2 Timing Control)
- * [23:22] reserved
- * [29:24] WrDatTimeByte3 (Write Data Byte 3 Timing Control)
- * [31:30] reserved
- */
- 0x01, 0xc0c0c0c0, 0x00000000,
- 0x21, 0xc0c0c0c0, 0x00000000,
- /* Write Data Timing High Control Register
- * Index 0x02
- * [ 5: 0] WrDatTimeByte4 (Write Data Byte 4 Timing Control)
- * [ 7: 6] reserved
- * [13: 8] WrDatTimeByte5 (Write Data Byte 5 Timing Control)
- * [15:14] reserved
- * [21:16] WrDatTimeByte6 (Write Data Byte 6 Timing Control)
- * [23:22] reserved
- * [29:24] WrDatTimeByte7 (Write Data Byte 7 Timing Control)
- * [31:30] reserved
- */
- 0x02, 0xc0c0c0c0, 0x00000000,
- 0x22, 0xc0c0c0c0, 0x00000000,
-
- /* Write Data ECC Timing Control Register
- * Index 0x03
- * [ 5: 0] WrChkTime (Write Data ECC Timing Control)
- * 000000 = no delay
- * 000001 = 1/96 MEMCLK delay
- * 000010 = 2/96 MEMCLK delay
- * ...
- * 101111 = 47/96 MEMCLK delay
- * 11xxxx = reserved
- * [31: 6] reserved
- */
- 0x03, 0x000000c0, 0x00000000,
- 0x23, 0x000000c0, 0x00000000,
-
- /* Address Timing Control Register
- * Index 0x04
- * [ 4: 0] CkeFineDelay (CKE Fine Delay)
- * 00000 = no delay
- * 00001 = 1/64 MEMCLK delay
- * 00010 = 2/64 MEMCLK delay
- * ...
- * 11111 = 31/64 MEMCLK delay
- * [ 5: 5] CkeSetup (CKE Setup Time)
- * 0 = 1/2 MEMCLK
- * 1 = 1 MEMCLK
- * [ 7: 6] reserved
- * [12: 8] CsOdtFineDelay (CS/ODT Fine Delay)
- * 00000 = no delay
- * 00001 = 1/64 MEMCLK delay
- * 00010 = 2/64 MEMCLK delay
- * ...
- * 11111 = 31/64 MEMCLK delay
- * [13:13] CsOdtSetup (CS/ODT Setup Time)
- * 0 = 1/2 MEMCLK
- * 1 = 1 MEMCLK
- * [15:14] reserved
- * [20:16] AddrCmdFineDelay (Address/Command Fine Delay)
- * 00000 = no delay
- * 00001 = 1/64 MEMCLK delay
- * 00010 = 2/64 MEMCLK delay
- * ...
- * 11111 = 31/64 MEMCLK delay
- * [21:21] AddrCmdSetup (Address/Command Setup Time)
- * 0 = 1/2 MEMCLK
- * 1 = 1 MEMCLK
- * [31:22] reserved
- */
- 0x04, 0xffc0c0c0, 0x00000000,
- 0x24, 0xffc0c0c0, 0x00000000,
-
- /* Read DQS Timing Low Control Register
- * Index 0x05
- * [ 5: 0] RdDqsTimeByte0 (Read DQS Byte 0 Timing Control)
- * 000000 = no delay
- * 000001 = 1/96 MEMCLK delay
- * 000010 = 2/96 MEMCLK delay
- * ...
- * 101111 = 47/96 MEMCLK delay
- * 11xxxx = reserved
- * [ 7: 6] reserved
- * [13: 8] RdDqsTimeByte1 (Read DQS Byte 1 Timing Control)
- * [15:14] reserved
- * [21:16] RdDqsTimeByte2 (Read DQS Byte 2 Timing Control)
- * [23:22] reserved
- * [29:24] RdDqsTimeByte3 (Read DQS Byte 3 Timing Control)
- * [31:30] reserved
- */
- 0x05, 0xc0c0c0c0, 0x00000000,
- 0x25, 0xc0c0c0c0, 0x00000000,
-
- /* Read DQS Timing High Control Register
- * Index 0x06
- * [ 5: 0] RdDqsTimeByte4 (Read DQS Byte 4 Timing Control)
- * [ 7: 6] reserved
- * [13: 8] RdDqsTimeByte5 (Read DQS Byte 5 Timing Control)
- * [15:14] reserved
- * [21:16] RdDqsTimeByte6 (Read DQS Byte 6 Timing Control)
- * [23:22] reserved
- * [29:24] RdDqsTimeByte7 (Read DQS Byte 7 Timing Control)
- * [31:30] reserved
- */
- 0x06, 0xc0c0c0c0, 0x00000000,
- 0x26, 0xc0c0c0c0, 0x00000000,
-
- /* Read DQS ECC Timing Control Register
- * Index 0x07
- * [ 5: 0] RdDqsTimeCheck (Read DQS ECC Timing Control)
- * 000000 = no delay
- * 000001 = 1/96 MEMCLK delay
- * 000010 = 2/96 MEMCLK delay
- * ...
- * 101111 = 47/96 MEMCLK delay
- * 11xxxx = reserved
- * [31: 6] reserved
- */
- 0x07, 0x000000c0, 0x00000000,
- 0x27, 0x000000c0, 0x00000000,
-
- /* DQS Receiver Enable Timing Control Register
- * Index 0x10, 0x13, 0x16, 0x19,
- * [ 7: 0] Dqs RcvEnDelay (DQS Receiver Enable Delay)
- * 0x00 = 0 ps
- * 0x01 = 50 ps
- * 0x02 = 100 ps
- * ...
- * 0xae = 8.7 ns
- * 0xaf-0xff = reserved
- * [31: 6] reserved
- */
- 0x10, 0x000000ff, 0x00000000,
- 0x13, 0x000000ff, 0x00000000,
- 0x16, 0x000000ff, 0x00000000,
- 0x19, 0x000000ff, 0x00000000,
- 0x30, 0x000000ff, 0x00000000,
- 0x33, 0x000000ff, 0x00000000,
- 0x36, 0x000000ff, 0x00000000,
- 0x39, 0x000000ff, 0x00000000,
- };
-#endif