projects
/
coreboot.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
remove trailing whitespace
[coreboot.git]
/
src
/
northbridge
/
amd
/
amdk8
/
raminit_f.c
diff --git
a/src/northbridge/amd/amdk8/raminit_f.c
b/src/northbridge/amd/amdk8/raminit_f.c
index 6652783e6648b9478d49a931ae0eece00962b282..319293b7ed61e9f138efeb6e261d57040e8ab19e 100644
(file)
--- a/
src/northbridge/amd/amdk8/raminit_f.c
+++ b/
src/northbridge/amd/amdk8/raminit_f.c
@@
-26,17
+26,16
@@
#include <stdlib.h>
#include "raminit.h"
#include <stdlib.h>
#include "raminit.h"
-#include "
amdk8_
f.h"
+#include "f.h"
#include <spd_ddr2.h>
#include <spd_ddr2.h>
-
-#ifndef QRANK_DIMM_SUPPORT
-#define QRANK_DIMM_SUPPORT 0
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
#endif
#if CONFIG_DEBUG_RAM_SETUP
#endif
#if CONFIG_DEBUG_RAM_SETUP
-#define printk_raminit(
fmt, arg...) printk(BIOS_DEBUG, fmt, arg
)
+#define printk_raminit(
args...) printk(BIOS_DEBUG, args
)
#else
#else
-#define printk_raminit(
fmt, arg
...)
+#define printk_raminit(
args
...)
#endif
#endif
@@
-44,7
+43,7
@@
# error "CONFIG_RAMTOP must be a power of 2"
#endif
# error "CONFIG_RAMTOP must be a power of 2"
#endif
-#include "
amdk8_
f_pci.c"
+#include "f_pci.c"
/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
@@
-74,7
+73,7
@@
*/
*/
-
static
void setup_resource_map(const unsigned int *register_values, int max)
+void setup_resource_map(const unsigned int *register_values, int max)
{
int i;
for (i = 0; i < max; i += 3) {
{
int i;
for (i = 0; i < max; i += 3) {
@@
-867,7
+866,7
@@
static void set_dimm_size(const struct mem_controller *ctrl,
/* Set the appropriate DIMM base address register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
/* Set the appropriate DIMM base address register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
-#if
QRANK_DIMM_SUPPORT == 1
+#if
CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
if (sz->rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
@@
-895,7
+894,7
@@
static void set_dimm_size(const struct mem_controller *ctrl,
} else {
dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
dword &= ~(ClkDis0 >> index);
} else {
dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
dword &= ~(ClkDis0 >> index);
-#if
QRANK_DIMM_SUPPORT == 1
+#if
CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
@@
-905,7
+904,7
@@
static void set_dimm_size(const struct mem_controller *ctrl,
if (meminfo->is_Width128) { // ChannelA+B
dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
dword &= ~(ClkDis0 >> index);
if (meminfo->is_Width128) { // ChannelA+B
dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
dword &= ~(ClkDis0 >> index);
-#if
QRANK_DIMM_SUPPORT == 1
+#if
CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
@@
-958,7
+957,7
@@
static void set_dimm_cs_map(const struct mem_controller *ctrl,
}
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
}
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
-#if
QRANK_DIMM_SUPPORT == 1
+#if
CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
if (sz->rank == 4) {
map &= ~(0xf << ( (index + 2) * 4));
}
@@
-969,7
+968,7
@@
static void set_dimm_cs_map(const struct mem_controller *ctrl,
unsigned temp_map;
temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
map |= temp_map << (index*4);
unsigned temp_map;
temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
map |= temp_map << (index*4);
-#if
QRANK_DIMM_SUPPORT == 1
+#if
CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
map |= temp_map << ( (index + 2) * 4);
}
if (sz->rank == 4) {
map |= temp_map << ( (index + 2) * 4);
}
@@
-1108,6
+1107,15
@@
static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
/* See if all of the memory chip selects are the same size
* and if so count them.
*/
/* See if all of the memory chip selects are the same size
* and if so count them.
*/
+#if defined(CMOS_VSTART_interleave_chip_selects)
+ if (read_option(interleave_chip_selects, 1) == 0)
+ return 0;
+#else
+#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || !CONFIG_INTERLEAVE_CHIP_SELECTS
+ return 0;
+#endif
+#endif
+
chip_selects = 0;
common_size = 0;
common_cs_mode = 0xff;
chip_selects = 0;
common_size = 0;
common_cs_mode = 0xff;
@@
-1280,15
+1288,10
@@
static void order_dimms(const struct mem_controller *ctrl,
{
unsigned long tom_k, base_k;
{
unsigned long tom_k, base_k;
- if (read_option(CMOS_VSTART_interleave_chip_selects,
- CMOS_VLEN_interleave_chip_selects, 1) != 0) {
- tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
- } else {
- printk(BIOS_DEBUG, "Interleaving disabled\n");
- tom_k = 0;
- }
+ tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
if (!tom_k) {
if (!tom_k) {
+ printk(BIOS_DEBUG, "Interleaving disabled\n");
tom_k = order_chip_selects(ctrl);
}
tom_k = order_chip_selects(ctrl);
}
@@
-1309,7
+1312,7
@@
static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
} else {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
} else {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
-#if
QRANK_DIMM_SUPPORT == 1
+#if
CONFIG_QRANK_DIMM_SUPPORT
if (meminfo->sz[index].rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
if (meminfo->sz[index].rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
@@
-1802,7
+1805,17
@@
static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
- read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
+#ifdef CMOS_VSTART_max_mem_clock
+ read_option(max_mem_clock, 0)
+#else
+#if defined(CONFIG_MAX_MEM_CLOCK)
+ CONFIG_MAX_MEM_CLOCK
+#else
+ 0 // use DDR400 as default
+#endif
+#endif
+ ];
+
if (bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time;
}
if (bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time;
}
@@
-2191,7
+2204,7
@@
static int update_dimm_Tref(const struct mem_controller *ctrl,
static void set_4RankRDimm(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
static void set_4RankRDimm(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
-#if
QRANK_DIMM_SUPPORT == 1
+#if
CONFIG_QRANK_DIMM_SUPPORT
int value;
int i;
long dimm_mask = meminfo->dimm_mask;
int value;
int i;
long dimm_mask = meminfo->dimm_mask;
@@
-2231,7
+2244,7
@@
static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
uint32_t mask_single_rank;
uint32_t mask_page_1k;
int value;
uint32_t mask_single_rank;
uint32_t mask_page_1k;
int value;
-#if
QRANK_DIMM_SUPPORT == 1
+#if
CONFIG_QRANK_DIMM_SUPPORT
int rank;
#endif
int rank;
#endif
@@
-2264,20
+2277,20
@@
static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
- #if
QRANK_DIMM_SUPPORT == 1
+ #if
CONFIG_QRANK_DIMM_SUPPORT
rank = meminfo->sz[i].rank;
#endif
if (value==4) {
mask_x4 |= (1<<i);
rank = meminfo->sz[i].rank;
#endif
if (value==4) {
mask_x4 |= (1<<i);
- #if
QRANK_DIMM_SUPPORT == 1
+ #if
CONFIG_QRANK_DIMM_SUPPORT
if (rank==4) {
mask_x4 |= 1<<(i+2);
}
#endif
} else if (value==16) {
mask_x16 |= (1<<i);
if (rank==4) {
mask_x4 |= 1<<(i+2);
}
#endif
} else if (value==16) {
mask_x16 |= (1<<i);
- #if
QRANK_DIMM_SUPPORT == 1
+ #if
CONFIG_QRANK_DIMM_SUPPORT
if (rank==4) {
mask_x16 |= 1<<(i+2);
}
if (rank==4) {
mask_x16 |= 1<<(i+2);
}
@@
-2361,14
+2374,21
@@
static void set_ecc(const struct mem_controller *ctrl,
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
}
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
}
- if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+#ifdef CMOS_VSTART_ECC_memory
+ if (read_option(ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn;
}
dcl &= ~DCL_DimmEccEn;
}
+#else // CMOS_VSTART_ECC_memory not defined
+#if !CONFIG_ECC_MEMORY
+ dcl &= ~DCL_DimmEccEn;
+#endif
+#endif
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
meminfo->is_ecc = 1;
if (!(dcl & DCL_DimmEccEn)) {
meminfo->is_ecc = 0;
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
meminfo->is_ecc = 1;
if (!(dcl & DCL_DimmEccEn)) {
meminfo->is_ecc = 0;
+ printk(BIOS_DEBUG, "set_ecc: ECC disabled\n");
return; // already disabled the ECC, so don't need to read SPD any more
}
return; // already disabled the ECC, so don't need to read SPD any more
}
@@
-2410,7
+2430,7
@@
static void set_TT(const struct mem_controller *ctrl,
uint32_t reg;
if ((val < TT_MIN) || (val > TT_MAX)) {
uint32_t reg;
if ((val < TT_MIN) || (val > TT_MAX)) {
- printk(BIOS_ERR, str);
+ printk(BIOS_ERR,
"%s",
str);
die(" Unknown\n");
}
die(" Unknown\n");
}
@@
-2989,14
+3009,15
@@
static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
}
#endif
}
#endif
-
+#if CONFIG_HAVE_ACPI_RESUME == 1
#include "exit_from_self.c"
#include "exit_from_self.c"
+#endif
static void sdram_enable(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo)
{
int i;
static void sdram_enable(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo)
{
int i;
-#if
def ACPI_IS_WAKEUP_EARLY
+#if
CONFIG_HAVE_ACPI_RESUME == 1
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
@@
-3206,7
+3227,7
@@
static void sdram_enable(int controllers, const struct mem_controller *ctrl,
}
}
-
static
void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
+void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
const uint16_t *spd_addr)
{
int i;
const uint16_t *spd_addr)
{
int i;