- wrmsr_smp(MSR_MTRRfix16K_A0000, 0);
- wrmsr_smp(MSR_MTRRfix4K_C0000, 0);
- wrmsr_smp(MSR_MTRRfix4K_C8000, 0);
- wrmsr_smp(MSR_MTRRfix4K_D0000, 0);
- wrmsr_smp(MSR_MTRRfix4K_D8000, 0);
- wrmsr_smp(MSR_MTRRfix4K_E0000, 0);
- wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
- wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
- wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
+ wrmsr_smp(MSR_MTRRfix16K_A0000, 0); // 0xA0000-0xC0000 is uncached
+ int j;
+ for (j = 0; j < 8; j++) {
+ u.val = 0;
+ for (i = 0; i < 8; i++)
+ if (RamSize >= 0xC0000 + j * 0x8000 + 4096 * (i + 1))
+ u.valb[i] = MTRR_MEMTYPE_WP;
+ wrmsr_smp(MSR_MTRRfix4K_C0000 + j, u.val);
+ }
+
+ // Set variable MTRRs
+ int phys_bits = 36;
+ cpuid(0x80000000u, &eax, &ebx, &ecx, &edx);
+ if (eax >= 0x80000008) {
+ /* Get physical bits from leaf 0x80000008 (if available) */
+ cpuid(0x80000008u, &eax, &ebx, &ecx, &edx);
+ phys_bits = eax & 0xff;
+ }
+ u64 phys_mask = ((1ull << phys_bits) - 1);
+ for (i=0; i<vcnt; i++) {
+ wrmsr_smp(MTRRphysBase_MSR(i), 0);
+ wrmsr_smp(MTRRphysMask_MSR(i), 0);
+ }