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Simplify a few code chunks, fix whitespace and indentation.
[coreboot.git]
/
src
/
mainboard
/
tyan
/
s2892
/
romstage.c
diff --git
a/src/mainboard/tyan/s2892/romstage.c
b/src/mainboard/tyan/s2892/romstage.c
index b15fda2cc65af015fde72edf422657b1646b101f..2ab6d32090a3b2b1ca0a21fad1e1a34f4a7acd1a 100644
(file)
--- a/
src/mainboard/tyan/s2892/romstage.c
+++ b/
src/mainboard/tyan/s2892/romstage.c
@@
-1,9
+1,3
@@
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@
-12,38
+6,27
@@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <lib.h>
#include <console/console.h>
#include <lib.h>
-
+#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include <cpu/amd/model_fxx_rev.h>
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.
c
"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.
h
"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-53,13
+36,10
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
#include "resourcemap.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/dualcore/dualcore.c"
-
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+
//set GPIO to input mode
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
//set GPIO to input mode
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
@@
-68,13
+48,8
@@
static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@
-94,32
+69,27
@@
static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
(0xa<<3)|0, (0xa<<3)|
2, 0, 0,
-
(0xa<<3)|1, (0xa<<3)|
3, 0, 0,
+
DIMM0, DIMM
2, 0, 0,
+
DIMM1, DIMM
3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
#if CONFIG_MAX_PHYSICAL_CPUS > 1
-
(0xa<<3)|4, (0xa<<3)|
6, 0, 0,
-
(0xa<<3)|5, (0xa<<3)|
7, 0, 0,
+
DIMM4, DIMM
6, 0, 0,
+
DIMM5, DIMM
7, 0, 0,
#endif
};
int needs_reset;
#endif
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
}
sio_setup();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
// post_code(0x32);
@@
-142,9
+112,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@@
-162,4
+130,3
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
post_cache_as_ram();
}
-