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Drop excessive whitespace randomly sprinkled in romstage.c files.
[coreboot.git]
/
src
/
mainboard
/
tyan
/
s2875
/
romstage.c
diff --git
a/src/mainboard/tyan/s2875/romstage.c
b/src/mainboard/tyan/s2875/romstage.c
index 3d97099be5c775a88ba5839766903b58862b870d..275ff2720cca67d6bbe486be1365487408285db4 100644
(file)
--- a/
src/mainboard/tyan/s2875/romstage.c
+++ b/
src/mainboard/tyan/s2875/romstage.c
@@
-9,28
+9,24
@@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
-
+#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@
-61,20
+57,13
@@
static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/dualcore/dualcore.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@
-87,8
+76,8
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = {
(0xa<<3)|0, (0xa<<3)|
2, 0, 0 },
- .channel1 = {
(0xa<<3)|1, (0xa<<3)|
3, 0, 0 },
+ .channel0 = {
DIMM0, DIMM
2, 0, 0 },
+ .channel1 = {
DIMM1, DIMM
3, 0, 0 },
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
@@
-97,8
+86,8
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = {
(0xa<<3)|4, (0xa<<3)|
6, 0, 0 },
- .channel1 = {
(0xa<<3)|5, (0xa<<3)|
7, 0, 0 },
+ .channel0 = {
DIMM4, DIMM
6, 0, 0 },
+ .channel1 = {
DIMM5, DIMM
7, 0, 0 },
},
#endif
};
},
#endif
};