+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */
+ 0xFF, 0xFF, /* only values used by raminit.c are set */
+ [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */
+ [SPD_NUM_ROWS] = 0x0D, /* Number of row address bits [13] */
+ [SPD_NUM_COLUMNS] = 0x0A, /* Number of column address bits [10] */
+ [SPD_NUM_DIMM_BANKS] = 1, /* Number of module rows (banks) */
+ 0xFF, 0xFF, 0xFF,
+ [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */
+ 0xFF, 0xFF,
+ [SPD_REFRESH] = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */
+ [SPD_PRIMARY_SDRAM_WIDTH] = 64, /* SDRAM width (primary SDRAM) [64 bits] */
+ 0xFF, 0xFF, 0xFF,
+ [SPD_NUM_BANKS_PER_SDRAM] = 4, /* SDRAM device attributes, number of banks on SDRAM device */
+ [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */
+ 0xFF, 0xFF,
+ [SPD_MODULE_ATTRIBUTES] = 0x20, /* SDRAM module attributes [differential clk] */
+ [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */
+ [SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */
+ 0xFF,
+ [SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */
+ 0xFF,
+ [SPD_tRP] = 72, /* Min. row precharge time [18 ns in units of 0.25 ns] */
+ [SPD_tRRD] = 48, /* Min. row active to row active [12 ns in units of 0.25 ns] */
+ [SPD_tRCD] = 72, /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */
+ [SPD_tRAS] = 42, /* Min. RAS pulse width = active to precharge delay [42 ns] */
+ [SPD_BANK_DENSITY] = 0x40, /* Density of each row on module [256 MB] */
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ [SPD_tRFC] = 72 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */
+};
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)