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Drop excessive whitespace randomly sprinkled in romstage.c files.
[coreboot.git]
/
src
/
mainboard
/
intel
/
eagleheights
/
romstage.c
diff --git
a/src/mainboard/intel/eagleheights/romstage.c
b/src/mainboard/intel/eagleheights/romstage.c
index 774f88f60f027c5ae01a5f90569796b4249d59ab..82064a418c0164884ce40bafd37536341d36ea36 100644
(file)
--- a/
src/mainboard/intel/eagleheights/romstage.c
+++ b/
src/mainboard/intel/eagleheights/romstage.c
@@
-21,36
+21,27
@@
*/
#include <delay.h>
*/
#include <delay.h>
-
#include <stdint.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <stdint.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-
#include <pc80/mc146818rtc.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/acpi.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/acpi.h>
-
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "reset.c"
#include "superio/intel/i3100/i3100_early_serial.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i3100/i3100.h"
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "reset.c"
#include "superio/intel/i3100/i3100_early_serial.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i3100/i3100.h"
+#include "southbridge/intel/i3100/i3100.h"
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-/* SATA */
-#define SATA_MAP 0x90
-
-#define SATA_MODE_IDE 0x00
-#define SATA_MODE_AHCI 0x01
-
#define RCBA_RPC 0x0224 /* 32 bit */
#define RCBA_TCTL 0x3000 /* 8 bit */
#define RCBA_RPC 0x0224 /* 32 bit */
#define RCBA_TCTL 0x3000 /* 8 bit */
@@
-83,6
+74,7
@@
static inline int spd_read_byte(u16 device, u8 address)
#include "lib/generic_sdram.c"
#include "northbridge/intel/i3100/reset_test.c"
#include "debug.c"
#include "lib/generic_sdram.c"
#include "northbridge/intel/i3100/reset_test.c"
#include "debug.c"
+#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
@@
-141,8
+133,8
@@
void main(unsigned long bist)
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
- .channel0 = {
(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|
0 },
- .channel1 = {
(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|
4 },
+ .channel0 = {
DIMM3, DIMM2, DIMM1, DIMM
0 },
+ .channel1 = {
DIMM7, DIMM6, DIMM5, DIMM
4 },
}
};
}
};
@@
-200,4
+192,3
@@
void main(unsigned long bist)
/* Initialize memory */
sdram_initialize(ARRAY_SIZE(mch), mch);
}
/* Initialize memory */
sdram_initialize(ARRAY_SIZE(mch), mch);
}
-