projects
/
coreboot.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
remove trailing whitespace
[coreboot.git]
/
src
/
mainboard
/
getac
/
p470
/
romstage.c
diff --git
a/src/mainboard/getac/p470/romstage.c
b/src/mainboard/getac/p470/romstage.c
index 270a7bd578745f539cdebf2c090d43cd921cadcf..afad4bc82093d83633051410c340f935395aaae8 100644
(file)
--- a/
src/mainboard/getac/p470/romstage.c
+++ b/
src/mainboard/getac/p470/romstage.c
@@
-1,6
+1,6
@@
/*
* This file is part of the coreboot project.
/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@@
-27,7
+27,6
@@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
-#include <usbdebug.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
@@
-83,7
+82,7
@@
void setup_ich7_gpios(void)
static void ich7_enable_lpc(void)
{
int lpt_en = 0;
static void ich7_enable_lpc(void)
{
int lpt_en = 0;
- if (read_option(
CMOS_VSTART_lpt, CMOS_VLEN_
lpt, 0) != 0) {
+ if (read_option(lpt, 0) != 0) {
lpt_en = 1<<2; // enable LPT
}
// Enable Serial IRQ
lpt_en = 1<<2; // enable LPT
}
// Enable Serial IRQ
@@
-286,12
+285,6
@@
void main(unsigned long bist)
early_superio_config();
/* Set up the console */
early_superio_config();
/* Set up the console */
- uart_init();
-
-#if CONFIG_USBDEBUG
- i82801gx_enable_usbdebug(1);
- early_usbdebug_init();
-#endif
console_init();
/* Halt if there was a built in self test failure */
console_init();
/* Halt if there was a built in self test failure */
@@
-327,18
+320,18
@@
void main(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-
+
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode
, NULL
);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
/* Perform some initialization that must run before stage2 */
early_ich7_init();
- /* This should probably go away. Until now it is required
- * and mainboard specific
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
*/
rcba_config();
*/
rcba_config();
@@
-380,11
+373,11
@@
void main(unsigned long bist)
* memory completely, but that's a wonderful clean up task for another
* day.
*/
* memory completely, but that's a wonderful clean up task for another
* day.
*/
- if (resume_backup_memory)
+ if (resume_backup_memory)
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
0xcafed00d
);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
SKPAD_ACPI_S3_MAGIC
);
}
#endif
}
}
#endif
}