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Remove comments that are obsolete since r6028.
[coreboot.git]
/
src
/
mainboard
/
asus
/
m2v-mx_se
/
romstage.c
diff --git
a/src/mainboard/asus/m2v-mx_se/romstage.c
b/src/mainboard/asus/m2v-mx_se/romstage.c
index 2514019aa6badb48e16bf8eb259a68737c0e260b..f252b3d220ff1207b5c91969434209efea75a5f8 100644
(file)
--- a/
src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/
src/mainboard/asus/m2v-mx_se/romstage.c
@@
-5,7
+5,7
@@
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
* Copyright (C) 2006 MSI
* (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
* Copyright (C) 2006 MSI
* (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@
-22,20
+22,13
@@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RAMINIT_SYSINFO 1
-
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
unsigned int get_sbdn(unsigned bus);
unsigned int get_sbdn(unsigned bus);
-/* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
-
/* Used by init_cpus and fidvid */
/* Used by init_cpus and fidvid */
-#define
K8_
SET_FIDVID 1
+#define SET_FIDVID 1
/* If we want to wait for core1 done before DQS training, set it to 0. */
/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define
K8_
SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@
-49,31
+42,23
@@
unsigned int get_sbdn(unsigned bus);
#include <arch/romcc_io.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/lapic.h>
#include <arch/romcc_io.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/early_ht.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "cpu/
amd/mtrr/amd_
earlymtrr.c"
+#include "cpu/
x86/mtrr/
earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-static void memreset_setup(void)
-{
-}
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@
-83,20
+68,21
@@
static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
return smbus_read_byte(device, address);
}
-void activate_spd_rom(const struct mem_controller *ctrl)
+
static
void activate_spd_rom(const struct mem_controller *ctrl)
{
}
{
}
-#define K8_4RANK_DIMM_SUPPORT 1
-
+// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "southbridge/via/k8t890/k8t890_early_car.c"
+
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/raminit_f.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "lib/generic_sdram.c"
+
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/copy_and_run.c"
+
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@
-105,29
+91,23
@@
void activate_spd_rom(const struct mem_controller *ctrl)
/* this function might fail on some K8 CPUs with errata #181 */
static void ldtstop_sb(void)
{
/* this function might fail on some K8 CPUs with errata #181 */
static void ldtstop_sb(void)
{
- print_debug("toggle LDTSTP#\
r\
n");
+ print_debug("toggle LDTSTP#\n");
u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
reg = reg ^ (1 << 0);
outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
reg = reg ^ (1 << 0);
outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
- print_debug("done\
r\
n");
+ print_debug("done\n");
}
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
}
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-#warning No hard_reset implemented for this board!
-void hard_reset(void)
-{
- print_info("NO HARD RESET. FIX ME!\n");
-}
-
void soft_reset(void)
{
uint8_t tmp;
set_bios_reset();
void soft_reset(void)
{
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset \
r\
n");
+ print_debug("soft reset \n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@
-150,37
+130,21
@@
unsigned int get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
return (dev >> 15) & 0x1f;
}
-void sio_init(void)
-{
-
-}
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- real_main(bist, cpu_init_detectedx);
-}
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- msr_t msr;
static const uint16_t spd_addr[] = {
static const uint16_t spd_addr[] = {
+ // Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-
#if CONFIG_MAX_PHYSICAL_CPUS >
1
+
// Node
1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- char *p;
- u8 reg;
+ (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- sio_init();
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
@@
-188,7
+152,7
@@
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
console_init();
enable_rom_decode();
- print
_info("now booting... real_main\r
\n");
+ print
k(BIOS_INFO, "now booting...
\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@
-199,7
+163,7
@@
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
setup_coherent_ht_domain();
wait_all_core0_started();
- print
_info("now booting... Core0 started\r
\n");
+ print
k(BIOS_INFO, "now booting... All core 0 started
\n");
#if CONFIG_LOGICAL_CPUS==1
/* It is said that we should start core1 after all core0 launched. */
#if CONFIG_LOGICAL_CPUS==1
/* It is said that we should start core1 after all core0 launched. */
@@
-220,12
+184,9
@@
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
vt8237_early_spi_init();
if (needs_reset) {
vt8237_early_spi_init();
if (needs_reset) {
- print_debug_hex8(needs_reset);
-
- print_debug("Xht reset -\r\n");
+ printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
soft_reset();
- print_debug("NO reset\r\n");
-
+ printk(BIOS_DEBUG, "FAILED!\n");
}
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
}
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
@@
-233,7
+194,7
@@
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
vt8237_sb_enable_fid_vid();
enable_fid_change();
vt8237_sb_enable_fid_vid();
enable_fid_change();
- print_debug("after enable_fid_change\
r\
n");
+ print_debug("after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
@@
-243,7
+204,6
@@
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
- memreset_setup();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}