+
+}
+
+static void print_cache_size(void)
+{
+ unsigned index;
+ unsigned int n, eax, ebx, ecx, edx;
+
+ index = 0x80000000;
+ printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ n = eax;
+
+ if (n >= 0x80000005) {
+ index = 0x80000005;
+ printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk(BIOS_DEBUG, "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
+ edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
+ }
+
+ if (n >= 0x80000006) {
+ index = 0x80000006;
+ printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk(BIOS_DEBUG, "CPU: L2 Cache: %dK (%d bytes/line)\n",
+ ecx >> 16, ecx & 0xFF);
+ }
+
+}
+
+struct tsc_struct {
+ unsigned lo;
+ unsigned hi;
+};
+typedef struct tsc_struct tsc_t;
+
+static tsc_t rdtsc(void)
+{
+ tsc_t res;
+ asm volatile(
+ "rdtsc"
+ : "=a" (res.lo), "=d"(res.hi) /* outputs */
+ );
+ return res;
+}
+
+static void print_tsc(void) {
+
+ tsc_t tsc;
+ tsc = rdtsc();
+ printk(BIOS_DEBUG, "tsc: 0x%08x%08x\n",
+ tsc.hi, tsc.lo);
+ udelay(1);
+ tsc = rdtsc();
+ printk(BIOS_DEBUG, "tsc: 0x%08x%08x after udelay(1) \n",
+ tsc.hi, tsc.lo);
+
+}
+
+static void debug_init(device_t dev)
+{
+ device_t parent;
+
+ if (!dev->enabled)
+ return;
+ switch(dev->path.pnp.device) {
+ case 0:
+ parent = dev->bus->dev;
+ printk(BIOS_DEBUG, "DEBUG: %s", dev_path(parent));
+ if(parent->chip_ops && parent->chip_ops->name) {
+ printk(BIOS_DEBUG, ": %s\n", parent->chip_ops->name);
+ } else {
+ printk(BIOS_DEBUG, "\n");
+ }
+ break;
+
+ case 1:
+ print_pci_regs_all();
+ break;
+ case 2:
+ print_mem();
+ break;
+ case 3:
+ print_cpuid();
+ break;
+ case 4:
+ print_smbus_regs_all(&dev_root);
+ break;
+ case 5:
+ print_msr_dualcore();
+ break;
+ case 6:
+ print_cache_size();
+ break;
+ case 7:
+ print_tsc();
+ break;
+ case 8:
+ hard_reset();
+ break;
+ }