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[hwmod.git]
/
src
/
beh_parser_tb.vhd
diff --git
a/src/beh_parser_tb.vhd
b/src/beh_parser_tb.vhd
index fc43bcf5303bc5dbdc2b155a8f6f12490de51d5f..b0626cf8cfc763035ef26366ab3e6545aec3411f 100644
(file)
--- a/
src/beh_parser_tb.vhd
+++ b/
src/beh_parser_tb.vhd
@@
-10,15
+10,8
@@
architecture sim of beh_parser_tb is
-- system
signal sys_clk, sys_res_n : std_logic;
-- history
-- system
signal sys_clk, sys_res_n : std_logic;
-- history
- signal p_r
w, p_r
get, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
+ signal p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
signal p_read, p_write : hbyte;
signal p_read, p_write : hbyte;
- signal p_spalte : hspalte;
-
- -- alu
- signal opcode : alu_ops;
- signal op1, op2, op3 : csigned;
- signal do_calc, calc_done : std_logic;
-
--scanner
signal do_it : std_logic;
signal finished : std_logic;
--scanner
signal do_it : std_logic;
signal finished : std_logic;
@@
-30,8
+23,7
@@
begin
(
sys_clk => sys_clk,
sys_res_n => sys_res_n,
(
sys_clk => sys_clk,
sys_res_n => sys_res_n,
- p_rw => p_rw,
- p_spalte => p_spalte,
+ -- history
p_rget => p_rget,
p_rdone => p_rdone,
p_read => p_read,
p_rget => p_rget,
p_rdone => p_rdone,
p_read => p_read,
@@
-39,32
+31,11
@@
begin
p_wdone => p_wdone,
p_write => p_write,
p_finished => p_finished,
p_wdone => p_wdone,
p_write => p_write,
p_finished => p_finished,
- -- ALU
- opcode => opcode,
- op1 => op1,
- op2 => op2,
- op3 => op3,
- do_calc => do_calc,
- calc_done => calc_done,
- -- TODO: calc_error : in std_logic;
-- Scanner
do_it => do_it,
finished => finished
);
-- Scanner
do_it => do_it,
finished => finished
);
- instalu : entity work.alu(beh)
- port map
- (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
- do_calc => do_calc,
- calc_done => calc_done,
- op1 => op1,
- op2 => op2,
- op3 => op3,
- opcode => opcode
- );
-
process
begin
sys_clk <= '0';
process
begin
sys_clk <= '0';
@@
-85,10
+56,11
@@
begin
variable input : hstring;
variable expectedresult : hstring;
variable realresult : hstring;
variable input : hstring;
variable expectedresult : hstring;
variable realresult : hstring;
+ variable hstrtmp : hstring;
variable checkall : boolean := true;
variable run_tc : boolean := true;
variable checkall : boolean := true;
variable run_tc : boolean := true;
- variable i, j, k : natural;
+ variable i, j, k
, y
: natural;
begin
-- init & reset
sys_res_n <= '0';
begin
-- init & reset
sys_res_n <= '0';
@@
-102,11
+74,11
@@
begin
i := 1;
f_loop : while not endfile(f) loop
i := 1;
f_loop : while not endfile(f) loop
- realresult := (
others => character'val(0)
);
+ realresult := (
72 => nul, others => ' '
);
f1_loop : while not endfile(f) loop
readline (f, l);
f1_loop : while not endfile(f) loop
readline (f, l);
- input := (others =>
character'val(0)
);
+ input := (others =>
nul
);
if (l'length <= 72) then
input(1 to l'length) := l.all;
if (input(1) = '#') then
if (l'length <= 72) then
input(1 to l'length) := l.all;
if (input(1) = '#') then
@@
-122,12
+94,13
@@
begin
f2_loop : while not endfile(f) loop
readline (f, l);
f2_loop : while not endfile(f) loop
readline (f, l);
- expectedresult := (others =>
character'val(0)
);
+ expectedresult := (others =>
nul
);
if (l'length <= 72) then
expectedresult(1 to l'length) := l.all;
if (expectedresult(1) = '#') then
next f2_loop;
else
if (l'length <= 72) then
expectedresult(1 to l'length) := l.all;
if (expectedresult(1) = '#') then
next f2_loop;
else
+ y := l'length;
exit f2_loop;
end if;
else
exit f2_loop;
end if;
else
@@
-136,6
+109,16
@@
begin
end if;
end loop f2_loop;
end if;
end loop f2_loop;
+ -- ergebnis string richtig formatieren
+ hstrtmp := expectedresult;
+ expectedresult := (72 => nul, others => ' ');
+ for x in 1 to 71 loop
+ if hstrtmp(x) /= nul then
+ expectedresult((71-y) + x) := hstrtmp(x);
+ end if;
+ end loop;
+
+
report "testcase(" & natural'image(i) & ").input: " & input;
report "testcase(" & natural'image(i) & ").expectedresult: " & expectedresult;
i := i + 1;
report "testcase(" & natural'image(i) & ").input: " & input;
report "testcase(" & natural'image(i) & ").expectedresult: " & expectedresult;
i := i + 1;
@@
-143,7
+126,7
@@
begin
icwait(sys_clk, 5);
do_it <= '1';
run_tc := true;
icwait(sys_clk, 5);
do_it <= '1';
run_tc := true;
- j := 1; k := 1;
+ j := 1; k :=
7
1;
while run_tc loop
wait on p_rget, p_wtake, p_finished, finished;
while run_tc loop
wait on p_rget, p_wtake, p_finished, finished;
@@
-161,7
+144,7
@@
begin
if p_wtake = '1' then
realresult(k) := character'val(to_integer(unsigned(p_write)));
p_wdone <= '1';
if p_wtake = '1' then
realresult(k) := character'val(to_integer(unsigned(p_write)));
p_wdone <= '1';
- k := k
+
1;
+ k := k
-
1;
end if;
if p_wtake = '0' then
p_wdone <= '0';
end if;
if p_wtake = '0' then
p_wdone <= '0';
@@
-173,7
+156,7
@@
begin
end loop;
do_it <= '0';
end loop;
do_it <= '0';
- report "realresult: " & realresult;
+ report "realresult
: " & realresult;
if realresult /= expectedresult then
checkall := false;
end if;
if realresult /= expectedresult then
checkall := false;
end if;