- u32 port1, port2, irq;
- if (prog_if & 1) {
- port1 = pci_config_readl(bdf, PCI_BASE_ADDRESS_0) & ~3;
- port2 = pci_config_readl(bdf, PCI_BASE_ADDRESS_1) & ~3;
- irq = pciirq;
- } else {
- port1 = PORT_ATA1_CMD_BASE;
- port2 = PORT_ATA1_CTRL_BASE;
- irq = IRQ_ATA1;
- }
- init_controller(count, bdf, irq, port1, port2, master);
- count++;
-
- if (prog_if & 4) {
- port1 = pci_config_readl(bdf, PCI_BASE_ADDRESS_2) & ~3;
- port2 = pci_config_readl(bdf, PCI_BASE_ADDRESS_3) & ~3;
- irq = pciirq;
- } else {
- port1 = PORT_ATA2_CMD_BASE;
- port2 = PORT_ATA2_CTRL_BASE;
- irq = IRQ_ATA2;
- }
- init_controller(count, bdf, irq, port1, port2, master ? master + 8 : 0);
- count++;
+ u32 port1, port2, irq;
+ if (prog_if & 1) {
+ port1 = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
+ & PCI_BASE_ADDRESS_IO_MASK);
+ port2 = (pci_config_readl(bdf, PCI_BASE_ADDRESS_1)
+ & PCI_BASE_ADDRESS_IO_MASK);
+ irq = pciirq;
+ } else {
+ port1 = PORT_ATA1_CMD_BASE;
+ port2 = PORT_ATA1_CTRL_BASE;
+ irq = IRQ_ATA1;
+ }
+ init_controller(pci, irq, port1, port2, master);
+
+ if (prog_if & 4) {
+ port1 = (pci_config_readl(bdf, PCI_BASE_ADDRESS_2)
+ & PCI_BASE_ADDRESS_IO_MASK);
+ port2 = (pci_config_readl(bdf, PCI_BASE_ADDRESS_3)
+ & PCI_BASE_ADDRESS_IO_MASK);
+ irq = pciirq;
+ } else {
+ port1 = PORT_ATA2_CMD_BASE;
+ port2 = PORT_ATA2_CTRL_BASE;
+ irq = IRQ_ATA2;