Move SeaBIOS output out of coreboot source tree

[coreboot.git] / src / Kconfig

diff --git a/src/Kconfig b/src/Kconfig
index 026e99da78a14eb2e7cea15cf6c265071bb9931d..c165d932a7ee444fe3347567f5dc58e7533ad7d2 100644 (file)
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -80,10 +80,51 @@ config CCACHE
          Enables the use of ccache for faster builds.
          Requires ccache in path.
 
          Enables the use of ccache for faster builds.
          Requires ccache in path.
 

+config SCONFIG_GENPARSER
+       bool "Generate SCONFIG parser using flex and bison"
+       default n
+       depends on EXPERT
+       help
+         Enable this option if you are working on the sconfig
+         device tree parser and made changes to sconfig.l and
+         sconfig.y.
+         Otherwise, say N.
+
+config USE_OPTION_TABLE
+       bool "Use CMOS for configuration values"
+       default n
+       depends on HAVE_OPTION_TABLE
+       help
+         Enable this option if coreboot shall read options from the "CMOS"
+         NVRAM instead of using hard coded values.
+
+config COMPRESS_RAMSTAGE
+       bool "Compress ramstage with LZMA"
+       default y
+       help
+         Compress ramstage to save memory in the flash image. Note
+         that decompression might slow down booting if the boot flash
+         is connected through a slow Link (i.e. SPI)
+
+config INCLUDE_CONFIG_FILE
+  bool "Include the coreboot config file into the ROM image"
+       default y
+  help
+    Include in CBFS the coreboot config file that was used to compile the ROM image
+

 endmenu
 
 source src/mainboard/Kconfig
 endmenu
 
 source src/mainboard/Kconfig

-source src/arch/i386/Kconfig
+
+# This option is used to set the architecture of a mainboard to X86.
+# It is usually set in mainboard/*/Kconfig.
+config ARCH_X86
+       bool
+       default n
+
+if ARCH_X86
+source src/arch/x86/Kconfig
+endif

 
 menu "Chipset"
 
 
 menu "Chipset"
 


@@ -97,29 +138,19 @@ comment "Super I/O"
 source src/superio/Kconfig
 comment "Devices"
 source src/devices/Kconfig
 source src/superio/Kconfig
 comment "Devices"
 source src/devices/Kconfig

+comment "Embedded Controllers"
+source src/ec/Kconfig

 
 endmenu
 
 
 endmenu
 

+menu "Generic Drivers"
+source src/drivers/Kconfig
+endmenu
+

 config PCI_BUS_SEGN_BITS
        int
        default 0
 
 config PCI_BUS_SEGN_BITS
        int
        default 0
 

-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-       hex
-       default 0x0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-       hex
-       default 0x0
-
-config CPU_ADDR_BITS
-       int
-       default 36
-
-config LOGICAL_CPUS
-       bool
-       default y
-

 config PCI_ROM_RUN
        bool
        default n
 config PCI_ROM_RUN
        bool
        default n


@@ -128,18 +159,6 @@ config HEAP_SIZE
        hex
        default 0x4000
 
        hex
        default 0x4000
 

-config DEBUG
-       bool
-       default n
-
-config USE_PRINTK_IN_CAR
-       bool
-       default n
-
-config USE_OPTION_TABLE
-       bool "Use CMOS for configuration values"
-       default n
-

 config MAX_CPUS
        int
        default 1
 config MAX_CPUS
        int
        default 1


@@ -152,15 +171,25 @@ config MMCONF_SUPPORT
        bool
        default n
 
        bool
        default n
 

-config ATI_RAGE_XL
+source src/console/Kconfig
+
+# This should default to N and be set by SuperI/O drivers that have an UART
+config HAVE_UART_IO_MAPPED

        bool
        bool

+       default y

 
 

-source src/console/Kconfig
+config HAVE_UART_MEMORY_MAPPED
+       bool
+       default n

 
 config HAVE_ACPI_RESUME
        bool
        default n
 
 
 config HAVE_ACPI_RESUME
        bool
        default n
 

+config HAVE_ACPI_SLIC
+       bool
+       default n
+

 config ACPI_SSDTX_NUM
        int
        default 0
 config ACPI_SSDTX_NUM
        int
        default 0


@@ -182,13 +211,17 @@ config HAVE_MAINBOARD_RESOURCES
        bool
        default n
 
        bool
        default n
 

+config USE_OPTION_TABLE
+       bool
+       default n
+

 config HAVE_OPTION_TABLE
        bool
 config HAVE_OPTION_TABLE
        bool

-       default y
+       default n

        help
          This variable specifies whether a given board has a cmos.layout
          file containing NVRAM/CMOS bit definitions.
        help
          This variable specifies whether a given board has a cmos.layout
          file containing NVRAM/CMOS bit definitions.

-         It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
+         It defaults to 'n' but can be selected in mainboard/*/Kconfig.

 
 config PIRQ_ROUTE
        bool
 
 config PIRQ_ROUTE
        bool


@@ -232,27 +265,6 @@ config GFXUMA
 #
 # endmenu
 
 #
 # endmenu
 

-#TODO Remove this option or make it useful.
-config HAVE_LOW_TABLES
-       bool
-       default y
-       help
-         This Option is unused in the code.  Since two boards try to set it to
-         'n', they may be broken.  We either need to make the option useful or
-         get rid of it.  The broken boards are:
-         asus/m2v-mx_se
-         supermicro/h8dme
-
-config HAVE_HIGH_TABLES
-       bool
-       default y
-       help
-         This variable specifies whether a given northbridge has high table
-         support.
-         It is set in northbridge/*/Kconfig.
-         Whether or not the high tables are actually written by coreboot is
-         configurable by the user via WRITE_HIGH_TABLES.
-

 config HAVE_ACPI_TABLES
        bool
        help
 config HAVE_ACPI_TABLES
        bool
        help


@@ -292,15 +304,14 @@ config GENERATE_PIRQ_TABLE
        bool
        default HAVE_PIRQ_TABLE
 
        bool
        default HAVE_PIRQ_TABLE
 

-config WRITE_HIGH_TABLES
+config GENERATE_SMBIOS_TABLES

        bool
        bool

-       default HAVE_HIGH_TABLES
+       default y

 
 menu "System tables"
 
 config WRITE_HIGH_TABLES
        bool "Write 'high' tables to avoid being overwritten in F segment"
 
 menu "System tables"
 
 config WRITE_HIGH_TABLES
        bool "Write 'high' tables to avoid being overwritten in F segment"

-       depends on HAVE_HIGH_TABLES

        default y
 
 config MULTIBOOT
        default y
 
 config MULTIBOOT


@@ -335,13 +346,23 @@ config GENERATE_PIRQ_TABLE
 
          If unsure, say Y.
 
 
          If unsure, say Y.
 

+config GENERATE_SMBIOS_TABLES
+       depends on ARCH_X86
+       bool "Generate SMBIOS tables"
+       default y
+       help
+         Generate SMBIOS tables for this board.
+
+         If unsure, say Y.
+

 endmenu
 
 menu "Payload"
 
 choice
        prompt "Add a payload"
 endmenu
 
 menu "Payload"
 
 choice
        prompt "Add a payload"

-       default PAYLOAD_NONE
+       default PAYLOAD_NONE if !ARCH_X86
+       default PAYLOAD_SEABIOS if ARCH_X86

 
 config PAYLOAD_NONE
        bool "None"
 
 config PAYLOAD_NONE
        bool "None"


@@ -363,20 +384,77 @@ config PAYLOAD_ELF
          You will be able to specify the location and file name of the
          payload image later.
 
          You will be able to specify the location and file name of the
          payload image later.
 

+config PAYLOAD_SEABIOS
+       bool "SeaBIOS"
+       depends on ARCH_X86
+       help
+         Select this option if you want to build a coreboot image
+         with a SeaBIOS payload. If you don't know what this is
+         about, just leave it enabled.
+
+         See http://coreboot.org/Payloads for more information.
+
+config PAYLOAD_FILO
+       bool "FILO"
+       help
+         Select this option if you want to build a coreboot image
+         with a FILO payload. If you don't know what this is
+         about, just leave it enabled.
+
+         See http://coreboot.org/Payloads for more information.
+
+endchoice
+
+choice
+       prompt "SeaBIOS version"
+       default SEABIOS_STABLE
+       depends on PAYLOAD_SEABIOS
+
+config SEABIOS_STABLE
+       bool "stable"
+       help
+         Stable SeaBIOS version
+config SEABIOS_MASTER
+       bool "master"
+       help
+         Newest SeaBIOS version

 endchoice
 
 endchoice
 

-config FALLBACK_PAYLOAD_FILE
+choice
+       prompt "FILO version"
+       default FILO_STABLE
+       depends on PAYLOAD_FILO
+
+config FILO_STABLE
+       bool "0.6.0"
+       help
+         Stable FILO version
+config FILO_MASTER
+       bool "HEAD"
+       help
+         Newest FILO version
+endchoice
+
+config PAYLOAD_FILE

        string "Payload path and filename"
        depends on PAYLOAD_ELF
        default "payload.elf"
        help
          The path and filename of the ELF executable file to use as payload.
 
        string "Payload path and filename"
        depends on PAYLOAD_ELF
        default "payload.elf"
        help
          The path and filename of the ELF executable file to use as payload.
 

+config PAYLOAD_FILE
+       depends on PAYLOAD_SEABIOS
+       default "$(obj)/seabios/out/bios.bin.elf"
+
+config PAYLOAD_FILE
+       depends on PAYLOAD_FILO
+       default "payloads/external/FILO/filo/build/filo.elf"
+

 # TODO: Defined if no payload? Breaks build?
 config COMPRESSED_PAYLOAD_LZMA
        bool "Use LZMA compression for payloads"
        default y
 # TODO: Defined if no payload? Breaks build?
 config COMPRESSED_PAYLOAD_LZMA
        bool "Use LZMA compression for payloads"
        default y

-       depends on PAYLOAD_ELF
+       depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO

        help
          In order to reduce the size payloads take up in the ROM chip
          coreboot can compress them using the LZMA algorithm.
        help
          In order to reduce the size payloads take up in the ROM chip
          coreboot can compress them using the LZMA algorithm.


@@ -398,14 +476,14 @@ config VGA_BIOS
          You will be able to specify the location and file name of the
          image later.
 
          You will be able to specify the location and file name of the
          image later.
 

-config FALLBACK_VGA_BIOS_FILE
+config VGA_BIOS_FILE

        string "VGA BIOS path and filename"
        depends on VGA_BIOS
        default "vgabios.bin"
        help
          The path and filename of the file to use as VGA BIOS.
 
        string "VGA BIOS path and filename"
        depends on VGA_BIOS
        default "vgabios.bin"
        help
          The path and filename of the file to use as VGA BIOS.
 

-config FALLBACK_VGA_BIOS_ID
+config VGA_BIOS_ID

        string "VGA device PCI IDs"
        depends on VGA_BIOS
        default "1106,3230"
        string "VGA device PCI IDs"
        depends on VGA_BIOS
        default "1106,3230"


@@ -429,7 +507,7 @@ config INTEL_MBI
          You will be able to specify the location and file name of the
          image later.
 
          You will be able to specify the location and file name of the
          image later.
 

-config FALLBACK_MBI_FILE
+config MBI_FILE

        string "Intel MBI path and filename"
        depends on INTEL_MBI
        default "mbi.bin"
        string "Intel MBI path and filename"
        depends on INTEL_MBI
        default "mbi.bin"


@@ -438,40 +516,31 @@ config FALLBACK_MBI_FILE
 
 endmenu
 
 
 endmenu
 

-menu "Bootsplash"
-       depends on PCI_OPTION_ROM_RUN_YABEL
+menu "Display"
+       depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE

 
 

-config BOOTSPLASH
-       prompt "Show graphical bootsplash"
+config FRAMEBUFFER_SET_VESA_MODE
+       prompt "Set VESA framebuffer mode"

        bool
        bool

-       depends on PCI_OPTION_ROM_RUN_YABEL
-       help
-         This option shows a graphical bootsplash screen. The grapics are
-         loaded from the CBFS file bootsplash.jpg.
-
-config FALLBACK_BOOTSPLASH_FILE
-       string "Bootsplash path and filename"
-       depends on BOOTSPLASH
-       default "bootsplash.jpg"
+       depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE

        help
        help

-         The path and filename of the file to use as graphical bootsplash 
-         screen. The file format has to be jpg. 
+         Set VESA framebuffer mode (needed for bootsplash)

 
 # TODO: Turn this into a "choice".
 config FRAMEBUFFER_VESA_MODE
        prompt "VESA framebuffer video mode"
        hex
        default 0x117
 
 # TODO: Turn this into a "choice".
 config FRAMEBUFFER_VESA_MODE
        prompt "VESA framebuffer video mode"
        hex
        default 0x117

-       depends on BOOTSPLASH
+       depends on FRAMEBUFFER_SET_VESA_MODE

        help
        help

-         This option sets the resolution used for the coreboot framebuffer and
-         bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
+         This option sets the resolution used for the coreboot framebuffer (and
+         bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will

          some day make this a "choice".
 
          some day make this a "choice".
 

-config COREBOOT_KEEP_FRAMEBUFFER
+config FRAMEBUFFER_KEEP_VESA_MODE

        prompt "Keep VESA framebuffer"
        bool
        prompt "Keep VESA framebuffer"
        bool

-       depends on BOOTSPLASH
+       depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE

        help
          This option keeps the framebuffer mode set after coreboot finishes
          execution. If this option is enabled, coreboot will pass a
        help
          This option keeps the framebuffer mode set after coreboot finishes
          execution. If this option is enabled, coreboot will pass a


@@ -479,6 +548,21 @@ config COREBOOT_KEEP_FRAMEBUFFER
          framebuffer driver. If this option is disabled, coreboot will switch
          back to text mode before handing control to a payload.
 
          framebuffer driver. If this option is disabled, coreboot will switch
          back to text mode before handing control to a payload.
 

+config BOOTSPLASH
+       prompt "Show graphical bootsplash"
+       bool
+       depends on FRAMEBUFFER_SET_VESA_MODE
+       help
+         This option shows a graphical bootsplash screen. The grapics are
+         loaded from the CBFS file bootsplash.jpg.
+
+config BOOTSPLASH_FILE
+       string "Bootsplash path and filename"
+       depends on BOOTSPLASH
+       default "bootsplash.jpg"
+       help
+         The path and filename of the file to use as graphical bootsplash
+         screen. The file format has to be jpg.

 endmenu
 
 menu "Debugging"
 endmenu
 
 menu "Debugging"


@@ -489,21 +573,15 @@ config GDB_STUB
        default y
        help
          If enabled, you will be able to set breakpoints for gdb debugging.
        default y
        help
          If enabled, you will be able to set breakpoints for gdb debugging.

-         See src/arch/i386/lib/c_start.S for details.
+         See src/arch/x86/lib/c_start.S for details.
+
+config HAVE_DEBUG_RAM_SETUP
+       def_bool n

 
 config DEBUG_RAM_SETUP
        bool "Output verbose RAM init debug messages"
        default n
 
 config DEBUG_RAM_SETUP
        bool "Output verbose RAM init debug messages"
        default n

-       depends on (NORTHBRIDGE_AMD_AMDFAM10 \
-                || NORTHBRIDGE_AMD_AMDK8 \
-                || NORTHBRIDGE_VIA_CN700 \
-                || NORTHBRIDGE_VIA_CX700 \
-                || NORTHBRIDGE_VIA_VX800 \
-                || NORTHBRIDGE_INTEL_E7501 \
-                || NORTHBRIDGE_INTEL_I440BX \
-                || NORTHBRIDGE_INTEL_I82810 \
-                || NORTHBRIDGE_INTEL_I82830 \
-                || NORTHBRIDGE_INTEL_I945)
+       depends on HAVE_DEBUG_RAM_SETUP

        help
          This option enables additional RAM init related debug messages.
          It is recommended to enable this when debugging issues on your
        help
          This option enables additional RAM init related debug messages.
          It is recommended to enable this when debugging issues on your


@@ -513,15 +591,38 @@ config DEBUG_RAM_SETUP
 
          If unsure, say N.
 
 
          If unsure, say N.
 

+config HAVE_DEBUG_CAR
+       def_bool n
+
+config DEBUG_CAR
+       def_bool n
+       depends on HAVE_DEBUG_CAR
+
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+config DEBUG_CAR
+       bool "Output verbose Cache-as-RAM debug messages"
+       default n
+       depends on HAVE_DEBUG_CAR
+       help
+         This option enables additional CAR related debug messages.
+endif
+
+config DEBUG_PIRQ
+       bool "Check PIRQ table consistency"
+       default n
+       depends on GENERATE_PIRQ_TABLE
+       help
+         If unsure, say N.
+
+config HAVE_DEBUG_SMBUS
+       def_bool n
+

 config DEBUG_SMBUS
        bool "Output verbose SMBus debug messages"
        default n
 config DEBUG_SMBUS
        bool "Output verbose SMBus debug messages"
        default n

-       depends on (SOUTHBRIDGE_VIA_VT8237R \
-                || NORTHBRIDGE_VIA_VX800 \
-                || NORTHBRIDGE_VIA_CX700 \
-                || NORTHBRIDGE_AMD_AMDK8 \
-                || NORTHBRIDGE_AMD_AMDFAM10 \
-                || SOUTHBRIDGE_VIA_VT8231)
+       depends on HAVE_DEBUG_SMBUS

        help
          This option enables additional SMBus (and SPD) debug messages.
 
        help
          This option enables additional SMBus (and SPD) debug messages.
 


@@ -540,6 +641,71 @@ config DEBUG_SMI
 
          If unsure, say N.
 
 
          If unsure, say N.
 

+config DEBUG_SMM_RELOCATION
+       bool "Debug SMM relocation code"
+       default n
+       depends on HAVE_SMI_HANDLER
+       help
+         This option enables additional SMM handler relocation related
+         debug messages.
+
+         Note: This option will increase the size of the coreboot image.
+
+         If unsure, say N.
+
+config DEBUG_MALLOC
+       def_bool n
+
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+config DEBUG_MALLOC
+       bool "Output verbose malloc debug messages"
+       default n
+       help
+         This option enables additional malloc related debug messages.
+
+         Note: This option will increase the size of the coreboot image.
+
+         If unsure, say N.
+endif
+
+config DEBUG_ACPI
+       def_bool n
+
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+config DEBUG_ACPI
+       bool "Output verbose ACPI debug messages"
+       default n
+       help
+         This option enables additional ACPI related debug messages.
+
+         Note: This option will slightly increase the size of the coreboot image.
+
+         If unsure, say N.
+endif
+
+config REALMODE_DEBUG
+       def_bool n
+       depends on PCI_OPTION_ROM_RUN_REALMODE
+
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+config REALMODE_DEBUG
+       bool "Enable debug messages for option ROM execution"
+       default n
+       depends on PCI_OPTION_ROM_RUN_REALMODE
+       help
+         This option enables additional x86emu related debug messages.
+
+         Note: This option will increase the time to emulate a ROM.
+
+         If unsure, say N.
+endif
+

 config X86EMU_DEBUG
        bool "Output verbose x86emu debug messages"
        default n
 config X86EMU_DEBUG
        bool "Output verbose x86emu debug messages"
        default n


@@ -568,7 +734,7 @@ config X86EMU_DEBUG_TRACE
        depends on X86EMU_DEBUG
        help
          Print _all_ opcodes that are executed by x86emu.
        depends on X86EMU_DEBUG
        help
          Print _all_ opcodes that are executed by x86emu.

-         
+

          WARNING: This will produce a LOT of output and take a long time.
 
          Note: This option will increase the size of the coreboot image.
          WARNING: This will produce a LOT of output and take a long time.
 
          Note: This option will increase the size of the coreboot image.


@@ -683,8 +849,17 @@ config LLSHELL
        help
          If enabled, you will have a low level shell to examine your machine.
          Put llshell() in your (romstage) code to start the shell.
        help
          If enabled, you will have a low level shell to examine your machine.
          Put llshell() in your (romstage) code to start the shell.

-         See src/arch/i386/llshell/llshell.inc for details.
+         See src/arch/x86/llshell/llshell.inc for details.

 
 

+config TRACE
+       bool "Trace function calls"
+       default n
+       help
+         If enabled, every function will print information to console once
+         the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
+         the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
+         of calling function. Please note some printk releated functions
+         are omitted from trace to have good looking console dumps.

 endmenu
 
 config LIFT_BSP_APIC_ID
 endmenu
 
 config LIFT_BSP_APIC_ID


@@ -696,16 +871,55 @@ config AP_CODE_IN_CAR
        bool
        default n
 
        bool
        default n
 

+config RAMINIT_SYSINFO
+       bool
+       default n
+

 config ENABLE_APIC_EXT_ID
        bool
        default n
 
 config WARNINGS_ARE_ERRORS
        bool
 config ENABLE_APIC_EXT_ID
        bool
        default n
 
 config WARNINGS_ARE_ERRORS
        bool

-       default n
+       default y

 
 

-config ID_SECTION_OFFSET
-       hex
-       default 0x10
+# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
+# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
+# mutually exclusive. One of these options must be selected in the
+# mainboard Kconfig if the chipset supports enabling and disabling of
+# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
+# in mainboard/Kconfig to know if the button should be enabled or not.
+
+config POWER_BUTTON_DEFAULT_ENABLE
+       def_bool n
+       help
+         Select when the board has a power button which can optionally be
+         disabled by the user.
+
+config POWER_BUTTON_DEFAULT_DISABLE
+       def_bool n
+       help
+         Select when the board has a power button which can optionally be
+         enabled by the user, e.g. when the board ships with a jumper over
+         the power switch contacts.
+
+config POWER_BUTTON_FORCE_ENABLE
+       def_bool n
+       help
+         Select when the board requires that the power button is always
+         enabled.
+
+config POWER_BUTTON_FORCE_DISABLE
+       def_bool n
+       help
+         Select when the board requires that the power button is always
+         disabled, e.g. when it has been hardwired to ground.
+
+config POWER_BUTTON_IS_OPTIONAL
+       bool
+       default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
+       default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
+       help
+         Internal option that controls ENABLE_POWER_BUTTON visibility.

 
 source src/Kconfig.deprecated_options
 
 source src/Kconfig.deprecated_options