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top-level: weiteres portmapping fuer minimalsetup
[hwmod.git]
/
quartus
/
project_gen.tcl
diff --git
a/quartus/project_gen.tcl
b/quartus/project_gen.tcl
index 62d62a359b02894a3ffb849a3a53efb6d2a30cae..f8846a4e53bae87d086f1d1dfbe178fc367a507f 100644
(file)
--- a/
quartus/project_gen.tcl
+++ b/
quartus/project_gen.tcl
@@
-41,10
+41,12
@@
if {$make_assignments} {
#include source files
set_global_assignment -name TOP_LEVEL_ENTITY calc
set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
#include source files
set_global_assignment -name TOP_LEVEL_ENTITY calc
set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
- set_global_assignment -name VHDL_FILE ../../src/calc.vhd
set_global_assignment -name VHDL_FILE ../../src/alu.vhd
set_global_assignment -name VHDL_FILE ../../src/parser.vhd
set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
set_global_assignment -name VHDL_FILE ../../src/alu.vhd
set_global_assignment -name VHDL_FILE ../../src/parser.vhd
set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
+ set_global_assignment -name VHDL_FILE ../../src/display.vhd
+ set_global_assignment -name VHDL_FILE ../../src/history.vhd
+ set_global_assignment -name VHDL_FILE ../../src/calc.vhd
set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
#vga ip-core
set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
#vga ip-core