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3a_asm: FIX: parser fail bei labels aufloesen
[calu.git]
/
progs
/
deepjit.s
diff --git
a/progs/deepjit.s
b/progs/deepjit.s
index 2524ae10e125bb8926228171da4b6c460dddc15f..1436b63c6048139336aca09894acb6415eeb58d8 100644
(file)
--- a/
progs/deepjit.s
+++ b/
progs/deepjit.s
@@
-89,7
+89,7
@@
prog_imm:
.ifill push r6
prog_pop:
.ifill push r6
prog_pop:
-.ifill disc
r6
+.ifill disc
prog_xch:
.ifill pop r6
prog_xch:
.ifill pop r6
@@
-114,6
+114,11
@@
prog_not:
.define PBASE, 0x2030
.define PADDR, 0x4
.define PDATA, 0x8
.define PBASE, 0x2030
.define PADDR, 0x4
.define PDATA, 0x8
+.org 0
+start:
+ call main
+ call main
+ ret
main:
main:
@@
-125,52
+130,44
@@
u_recv_byte:
ldw r3, UART_STATUS(r10)
andx r3, UART_RECV_NEW
brzs+ u_recv_byte; branch if zero
ldw r3, UART_STATUS(r10)
andx r3, UART_RECV_NEW
brzs+ u_recv_byte; branch if zero
- xor r0, r0, r0
+
ldw r0, UART_RECV(r10)
;recv byte
ldw r0, UART_RECV(r10)
;recv byte
- ldi r0, 0x48
+ ldi
s
r0, 0x48
u_test:
ldw r9, UART_STATUS(r10)
andx r9, UART_TRANS_EMPTY
brnz+ u_test ; branch if not zero
stb r0, UART_TRANS(r10)
u_test:
ldw r9, UART_STATUS(r10)
andx r9, UART_TRANS_EMPTY
brnz+ u_test ; branch if not zero
stb r0, UART_TRANS(r10)
+
;set address of input
;set address of input
- ldi
l
r1, inputdata@lo
+ ldi
s
r1, inputdata@lo
ldih r1, inputdata@hi
ldih r1, inputdata@hi
+
;set address of program start
;set address of program start
- ldi
l r2, prog_start
@lo
- ldih r2,
prog_start
@hi
+ ldi
s r2, (prog_start/4)
@lo
+ ldih r2,
(prog_start/4)
@hi
;set address to instruction table
;set address to instruction table
- ldi
l
r3, instrtable@lo
+ ldi
s
r3, instrtable@lo
ldih r3, instrtable@hi
;set address to defer table
ldih r3, instrtable@hi
;set address to defer table
- ldi
l
r9, defertable@lo
+ ldi
s
r9, defertable@lo
ldih r9, defertable@hi
ldih r9, defertable@hi
- ldi
l
r13, PBASE@lo
+ ldi
s
r13, PBASE@lo
ldih r13, PBASE@hi
ldih r13, PBASE@hi
+
;set programmer address
stw r2, PADDR(r13)
;call jit compiler
call+ jit
;set programmer address
stw r2, PADDR(r13)
;call jit compiler
call+ jit
- ldi r10, UART_BASE@lo
- ldih r10, UART_BASE@hi
- ldi r0, 0x46
-u_panic:
- ldw r9, UART_STATUS(r10)
- andx r9, UART_TRANS_EMPTY
- brnz+ u_panic ; branch if not zero
- stb r0, UART_TRANS(r10)
-
-
-
;set address to stack
;ldil r3, stack@lo
;ldih r3, stack@hi
;set address to stack
;ldil r3, stack@lo
;ldih r3, stack@hi
@@
-184,12
+181,22
@@
u_panic:
call+ prog_start
;send result
call+ prog_start
;send result
-u_send_byte:
+ push r0
ldi r10, UART_BASE@lo
ldih r10, UART_BASE@hi
ldi r10, UART_BASE@lo
ldih r10, UART_BASE@hi
+
+u_send_byte1:
+ ldw r9, UART_STATUS(r10)
+ andx r9, UART_TRANS_EMPTY
+ brnz+ u_send_byte1 ; branch if not zero
+ ldis r0, 0x50
+ stb r0, UART_TRANS(r10)
+
+u_send_byte:
ldw r9, UART_STATUS(r10)
andx r9, UART_TRANS_EMPTY
brnz+ u_send_byte ; branch if not zero
ldw r9, UART_STATUS(r10)
andx r9, UART_TRANS_EMPTY
brnz+ u_send_byte ; branch if not zero
+ pop r0
stb r0, UART_TRANS(r10)
;send result
stb r0, UART_TRANS(r10)
;send result
@@
-272,7
+279,7
@@
vm_defer:
;generate branch
sub r11, r6, r8
;generate branch
sub r11, r6, r8
- lrs r11, r11, 2
+
;
lrs r11, r11, 2
;set the upper 16 bit 0
andx r11, 0xFFFF
;shift to the position of imm in br
;set the upper 16 bit 0
andx r11, 0xFFFF
;shift to the position of imm in br
@@
-319,7
+326,7
@@
vm_mul:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
52
+ addi r2, r2,
13
br+ vm_loop
br+ vm_loop
@@
-341,7
+348,7
@@
vm_add:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
16
+ addi r2, r2,
4
br+ vm_loop
br+ vm_loop
@@
-363,7
+370,7
@@
vm_sub:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
16
+ addi r2, r2,
4
br+ vm_loop
br+ vm_loop
@@
-389,7
+396,7
@@
vm_consts:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
8
+ addi r2, r2,
2
br+ vm_loop
br+ vm_loop
@@
-413,7
+420,7
@@
vm_lessthan:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
20
+ addi r2, r2,
5
br+ vm_loop
br+ vm_loop
@@
-430,7
+437,7
@@
vm_dup:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
8
+ addi r2, r2,
2
br+ vm_loop
br+ vm_loop
@@
-490,7
+497,7
@@
vm_imm:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
12
+ addi r2, r2,
3
;pc+4
addi r1, r1, 4
;pc+4
addi r1, r1, 4
@@
-524,7
+531,7
@@
vm_jmp:
PROGINSTR
;we add the offset to this instruction
PROGINSTR
;we add the offset to this instruction
- addi r8, r2,
12
+ addi r8, r2,
3
;we know calculate the jump destination
;we know calculate the jump destination
@@
-555,7
+562,7
@@
vm_jmp:
sub r8, r0, r8
;we shift 2 bits out, because rel. br takes instr.
;count and not address amount ...
sub r8, r0, r8
;we shift 2 bits out, because rel. br takes instr.
;count and not address amount ...
- lrs r8, r8, 2
+
;
lrs r8, r8, 2
;set the upper 16 bit 0
andx r8, 0xFFFF
;shift to the position of imm in br
;set the upper 16 bit 0
andx r8, 0xFFFF
;shift to the position of imm in br
@@
-566,7
+573,7
@@
vm_jmp:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
16
+ addi r2, r2,
4
br+ vm_loop
br+ vm_loop
@@
-592,7
+599,7
@@
vm_possign:
;increment defer table address
addi r9, r9, 8
;increment address
;increment defer table address
addi r9, r9, 8
;increment address
- addi r2, r2,
16
+ addi r2, r2,
4
br+ vm_loop
;case P
br+ vm_loop
;case P
@@
-607,7
+614,7
@@
vm_pop:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
4
+ addi r2, r2,
1
br+ vm_loop
br+ vm_loop
@@
-629,7
+636,7
@@
vm_xch:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
16
+ addi r2, r2,
4
br+ vm_loop
br+ vm_loop
@@
-649,7
+656,7
@@
vm_not:
PROGINSTR
;increment address
PROGINSTR
;increment address
- addi r2, r2,
12
+ addi r2, r2,
3
br+ vm_loop
br+ vm_loop
@@
-658,48
+665,48
@@
prog_start:
.data
jumptable:
;0
.data
jumptable:
;0
-.fill 1, vm_eof
-.fill 41, vm_default
+.fill 1, vm_eof
/4
+.fill 41, vm_default
/4
;42
;42
-.fill 1, vm_mul
+.fill 1, vm_mul
/4
;43
;43
-.fill 1, vm_add
+.fill 1, vm_add
/4
;44
;44
-.fill 1, vm_default
+.fill 1, vm_default
/4
;45
;45
-.fill 1, vm_sub
+.fill 1, vm_sub
/4
;46-47
;46-47
-.fill 2, vm_default
+.fill 2, vm_default
/4
;48-57
;48-57
-.fill 10, vm_consts
+.fill 10, vm_consts
/4
;58-59
;58-59
-.fill 2, vm_default
+.fill 2, vm_default
/4
;60
;60
-.fill 1, vm_lessthan
+.fill 1, vm_lessthan
/4
;61-67
;61-67
-.fill 7, vm_default
+.fill 7, vm_default
/4
;68
;68
-.fill 1, vm_dup
+.fill 1, vm_dup
/4
;69-72
;69-72
-.fill 4, vm_default
+.fill 4, vm_default
/4
;73
;73
-.fill 1, vm_imm
+.fill 1, vm_imm
/4
;74
;74
-.fill 1, vm_jmp
+.fill 1, vm_jmp
/4
;75-79
;75-79
-.fill 5, vm_default
+.fill 5, vm_default
/4
;80
;80
-.fill 1, vm_pop
+.fill 1, vm_pop
/4
;81-87
;81-87
-.fill 7, vm_default
+.fill 7, vm_default
/4
;88
;88
-.fill 1, vm_xch
+.fill 1, vm_xch
/4
;89-125
;89-125
-.fill 37, vm_default
+.fill 37, vm_default
/4
;126
;126
-.fill 1, vm_not
+.fill 1, vm_not
/4
;127-255
;127-255
-.fill 129, vm_default
+.fill 129, vm_default
/4
;we assume not more than 3 entries
defertable:
;we assume not more than 3 entries
defertable: