+static const SimdIntrinsc vector4i_intrinsics[] = {
+ { SN_ctor, OP_EXPAND_I4, SIMD_EMIT_CTOR },
+ { SN_CompareEqual, OP_PCMPEQD, SIMD_EMIT_BINARY },
+ { SN_CompareGreaterThan, OP_PCMPGTD, SIMD_EMIT_BINARY },
+ { SN_LoadAligned, 0, SIMD_EMIT_LOAD_ALIGNED },
+ { SN_LogicalRightShift, OP_PSHRD, SIMD_EMIT_SHIFT },
+ { SN_Max, OP_PMAXD, SIMD_EMIT_BINARY, SIMD_VERSION_SSE41 },
+ { SN_Min, OP_PMIND, SIMD_EMIT_BINARY, SIMD_VERSION_SSE41 },
+ { SN_PackWithSignedSaturation, OP_PACKD, SIMD_EMIT_BINARY },
+ { SN_PackWithUnsignedSaturation, OP_PACKD_UN, SIMD_EMIT_BINARY, SIMD_VERSION_SSE41 },
+ { SN_PrefetchTemporalAllCacheLevels, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_0 },
+ { SN_PrefetchTemporal1stLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_1 },
+ { SN_PrefetchTemporal2ndLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_2 },
+ { SN_PrefetchNonTemporal, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_NTA },
+ { SN_Shuffle, OP_PSHUFLED, SIMD_EMIT_SHUFFLE },
+ { SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, SIMD_EMIT_STORE },
+ { SN_UnpackHigh, OP_UNPACK_HIGHD, SIMD_EMIT_BINARY },
+ { SN_UnpackLow, OP_UNPACK_LOWD, SIMD_EMIT_BINARY },
+ { SN_get_W, 3, SIMD_EMIT_GETTER },
+ { SN_get_X, 0, SIMD_EMIT_GETTER },
+ { SN_get_Y, 1, SIMD_EMIT_GETTER },
+ { SN_get_Z, 2, SIMD_EMIT_GETTER },
+ { SN_op_Addition, OP_PADDD, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+ { SN_op_Equality, OP_PCMPEQD, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
+ { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
+ { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+ { SN_op_Inequality, OP_PCMPEQD, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
+ { SN_op_LeftShift, OP_PSHLD, SIMD_EMIT_SHIFT },
+ { SN_op_Multiply, OP_PMULD, SIMD_EMIT_BINARY, SIMD_VERSION_SSE41 },
+ { SN_op_RightShift, OP_PSARD, SIMD_EMIT_SHIFT },
+ { SN_op_Subtraction, OP_PSUBD, SIMD_EMIT_BINARY },
+ { SN_set_W, 3, SIMD_EMIT_SETTER },
+ { SN_set_X, 0, SIMD_EMIT_SETTER },
+ { SN_set_Y, 1, SIMD_EMIT_SETTER },
+ { SN_set_Z, 2, SIMD_EMIT_SETTER },
+};
+
+static const SimdIntrinsc vector8us_intrinsics[] = {
+ { SN_ctor, OP_EXPAND_I2, SIMD_EMIT_CTOR },
+ { SN_AddWithSaturation, OP_PADDW_SAT_UN, SIMD_EMIT_BINARY },
+ { SN_ArithmeticRightShift, OP_PSARW, SIMD_EMIT_SHIFT },
+ { SN_Average, OP_PAVGW_UN, SIMD_EMIT_BINARY },
+ { SN_CompareEqual, OP_PCMPEQW, SIMD_EMIT_BINARY },
+ { SN_LoadAligned, 0, SIMD_EMIT_LOAD_ALIGNED },
+ { SN_Max, OP_PMAXW_UN, SIMD_EMIT_BINARY, SIMD_VERSION_SSE41 },
+ { SN_Min, OP_PMINW_UN, SIMD_EMIT_BINARY, SIMD_VERSION_SSE41 },
+ { SN_MultiplyStoreHigh, OP_PMULW_HIGH_UN, SIMD_EMIT_BINARY },
+ { SN_PrefetchTemporalAllCacheLevels, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_0 },
+ { SN_PrefetchTemporal1stLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_1 },
+ { SN_PrefetchTemporal2ndLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_2 },
+ { SN_PrefetchNonTemporal, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_NTA },
+ { SN_ShuffleHigh, OP_PSHUFLEW_HIGH, SIMD_EMIT_SHUFFLE },
+ { SN_ShuffleLow, OP_PSHUFLEW_LOW, SIMD_EMIT_SHUFFLE },
+ { SN_SignedPackWithSignedSaturation, OP_PACKW, SIMD_EMIT_BINARY },
+ { SN_SignedPackWithUnsignedSaturation, OP_PACKW_UN, SIMD_EMIT_BINARY },
+ { SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, SIMD_EMIT_STORE },
+ { SN_SubtractWithSaturation, OP_PSUBW_SAT_UN, SIMD_EMIT_BINARY },
+ { SN_UnpackHigh, OP_UNPACK_HIGHW, SIMD_EMIT_BINARY },
+ { SN_UnpackLow, OP_UNPACK_LOWW, SIMD_EMIT_BINARY },
+ { SN_get_V0, 0, SIMD_EMIT_GETTER },
+ { SN_get_V1, 1, SIMD_EMIT_GETTER },
+ { SN_get_V2, 2, SIMD_EMIT_GETTER },
+ { SN_get_V3, 3, SIMD_EMIT_GETTER },
+ { SN_get_V4, 4, SIMD_EMIT_GETTER },
+ { SN_get_V5, 5, SIMD_EMIT_GETTER },
+ { SN_get_V6, 6, SIMD_EMIT_GETTER },
+ { SN_get_V7, 7, SIMD_EMIT_GETTER },
+ { SN_op_Addition, OP_PADDW, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+ { SN_op_Equality, OP_PCMPEQW, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
+ { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
+ { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+ { SN_op_Inequality, OP_PCMPEQW, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
+ { SN_op_LeftShift, OP_PSHLW, SIMD_EMIT_SHIFT },
+ { SN_op_Multiply, OP_PMULW, SIMD_EMIT_BINARY },
+ { SN_op_RightShift, OP_PSHRW, SIMD_EMIT_SHIFT },
+ { SN_op_Subtraction, OP_PSUBW, SIMD_EMIT_BINARY },
+ { SN_set_V0, 0, SIMD_EMIT_SETTER },
+ { SN_set_V1, 1, SIMD_EMIT_SETTER },
+ { SN_set_V2, 2, SIMD_EMIT_SETTER },
+ { SN_set_V3, 3, SIMD_EMIT_SETTER },
+ { SN_set_V4, 4, SIMD_EMIT_SETTER },
+ { SN_set_V5, 5, SIMD_EMIT_SETTER },
+ { SN_set_V6, 6, SIMD_EMIT_SETTER },
+ { SN_set_V7, 7, SIMD_EMIT_SETTER },
+};
+
+static const SimdIntrinsc vector8s_intrinsics[] = {
+ { SN_ctor, OP_EXPAND_I2, SIMD_EMIT_CTOR },
+ { SN_AddWithSaturation, OP_PADDW_SAT, SIMD_EMIT_BINARY },
+ { SN_CompareEqual, OP_PCMPEQW, SIMD_EMIT_BINARY },
+ { SN_CompareGreaterThan, OP_PCMPGTW, SIMD_EMIT_BINARY },
+ { SN_LoadAligned, 0, SIMD_EMIT_LOAD_ALIGNED },
+ { SN_LogicalRightShift, OP_PSHRW, SIMD_EMIT_SHIFT },
+ { SN_Max, OP_PMAXW, SIMD_EMIT_BINARY },
+ { SN_Min, OP_PMINW, SIMD_EMIT_BINARY },
+ { SN_MultiplyStoreHigh, OP_PMULW_HIGH, SIMD_EMIT_BINARY },
+ { SN_PackWithSignedSaturation, OP_PACKW, SIMD_EMIT_BINARY },
+ { SN_PackWithUnsignedSaturation, OP_PACKW_UN, SIMD_EMIT_BINARY },
+ { SN_PrefetchTemporalAllCacheLevels, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_0 },
+ { SN_PrefetchTemporal1stLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_1 },
+ { SN_PrefetchTemporal2ndLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_2 },
+ { SN_PrefetchNonTemporal, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_NTA },
+ { SN_ShuffleHigh, OP_PSHUFLEW_HIGH, SIMD_EMIT_SHUFFLE },
+ { SN_ShuffleLow, OP_PSHUFLEW_LOW, SIMD_EMIT_SHUFFLE },
+ { SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, SIMD_EMIT_STORE },
+ { SN_SubtractWithSaturation, OP_PSUBW_SAT_UN, SIMD_EMIT_BINARY },
+ { SN_UnpackHigh, OP_UNPACK_HIGHW, SIMD_EMIT_BINARY },
+ { SN_UnpackLow, OP_UNPACK_LOWW, SIMD_EMIT_BINARY },
+ { SN_get_V0, 0, SIMD_EMIT_GETTER },
+ { SN_get_V1, 1, SIMD_EMIT_GETTER },
+ { SN_get_V2, 2, SIMD_EMIT_GETTER },
+ { SN_get_V3, 3, SIMD_EMIT_GETTER },
+ { SN_get_V4, 4, SIMD_EMIT_GETTER },
+ { SN_get_V5, 5, SIMD_EMIT_GETTER },
+ { SN_get_V6, 6, SIMD_EMIT_GETTER },
+ { SN_get_V7, 7, SIMD_EMIT_GETTER },
+ { SN_op_Addition, OP_PADDW, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+ { SN_op_Equality, OP_PCMPEQW, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
+ { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
+ { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+ { SN_op_Inequality, OP_PCMPEQW, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
+ { SN_op_LeftShift, OP_PSHLW, SIMD_EMIT_SHIFT },
+ { SN_op_Multiply, OP_PMULW, SIMD_EMIT_BINARY },
+ { SN_op_RightShift, OP_PSARW, SIMD_EMIT_SHIFT },
+ { SN_op_Subtraction, OP_PSUBW, SIMD_EMIT_BINARY },
+ { SN_set_V0, 0, SIMD_EMIT_SETTER },
+ { SN_set_V1, 1, SIMD_EMIT_SETTER },
+ { SN_set_V2, 2, SIMD_EMIT_SETTER },
+ { SN_set_V3, 3, SIMD_EMIT_SETTER },
+ { SN_set_V4, 4, SIMD_EMIT_SETTER },
+ { SN_set_V5, 5, SIMD_EMIT_SETTER },
+ { SN_set_V6, 6, SIMD_EMIT_SETTER },
+ { SN_set_V7, 7, SIMD_EMIT_SETTER },
+};
+
+static const SimdIntrinsc vector16b_intrinsics[] = {
+ { SN_ctor, OP_EXPAND_I1, SIMD_EMIT_CTOR },
+ { SN_AddWithSaturation, OP_PADDB_SAT_UN, SIMD_EMIT_BINARY },
+ { SN_Average, OP_PAVGB_UN, SIMD_EMIT_BINARY },
+ { SN_CompareEqual, OP_PCMPEQB, SIMD_EMIT_BINARY },
+ { SN_ExtractByteMask, 0, SIMD_EMIT_EXTRACT_MASK },
+ { SN_LoadAligned, 0, SIMD_EMIT_LOAD_ALIGNED },
+ { SN_Max, OP_PMAXB_UN, SIMD_EMIT_BINARY },
+ { SN_Min, OP_PMINB_UN, SIMD_EMIT_BINARY },
+ { SN_PrefetchTemporalAllCacheLevels, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_0 },
+ { SN_PrefetchTemporal1stLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_1 },
+ { SN_PrefetchTemporal2ndLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_2 },
+ { SN_PrefetchNonTemporal, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_NTA },
+ { SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, SIMD_EMIT_STORE },
+ { SN_SubtractWithSaturation, OP_PSUBB_SAT_UN, SIMD_EMIT_BINARY },
+ { SN_SumOfAbsoluteDifferences, OP_PSUM_ABS_DIFF, SIMD_EMIT_BINARY },
+ { SN_UnpackHigh, OP_UNPACK_HIGHB, SIMD_EMIT_BINARY },
+ { SN_UnpackLow, OP_UNPACK_LOWB, SIMD_EMIT_BINARY },
+ { SN_get_V0, 0, SIMD_EMIT_GETTER },
+ { SN_get_V1, 1, SIMD_EMIT_GETTER },
+ { SN_get_V10, 10, SIMD_EMIT_GETTER },
+ { SN_get_V11, 11, SIMD_EMIT_GETTER },
+ { SN_get_V12, 12, SIMD_EMIT_GETTER },
+ { SN_get_V13, 13, SIMD_EMIT_GETTER },
+ { SN_get_V14, 14, SIMD_EMIT_GETTER },
+ { SN_get_V15, 15, SIMD_EMIT_GETTER },
+ { SN_get_V2, 2, SIMD_EMIT_GETTER },
+ { SN_get_V3, 3, SIMD_EMIT_GETTER },
+ { SN_get_V4, 4, SIMD_EMIT_GETTER },
+ { SN_get_V5, 5, SIMD_EMIT_GETTER },
+ { SN_get_V6, 6, SIMD_EMIT_GETTER },
+ { SN_get_V7, 7, SIMD_EMIT_GETTER },
+ { SN_get_V8, 8, SIMD_EMIT_GETTER },
+ { SN_get_V9, 9, SIMD_EMIT_GETTER },
+ { SN_op_Addition, OP_PADDB, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+ { SN_op_Equality, OP_PCMPEQB, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
+ { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
+ { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+ { SN_op_Inequality, OP_PCMPEQB, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
+ { SN_op_Subtraction, OP_PSUBB, SIMD_EMIT_BINARY },
+ { SN_set_V0, 0, SIMD_EMIT_SETTER },
+ { SN_set_V1, 1, SIMD_EMIT_SETTER },
+ { SN_set_V10, 10, SIMD_EMIT_SETTER },
+ { SN_set_V11, 11, SIMD_EMIT_SETTER },
+ { SN_set_V12, 12, SIMD_EMIT_SETTER },
+ { SN_set_V13, 13, SIMD_EMIT_SETTER },
+ { SN_set_V14, 14, SIMD_EMIT_SETTER },
+ { SN_set_V15, 15, SIMD_EMIT_SETTER },
+ { SN_set_V2, 2, SIMD_EMIT_SETTER },
+ { SN_set_V3, 3, SIMD_EMIT_SETTER },
+ { SN_set_V4, 4, SIMD_EMIT_SETTER },
+ { SN_set_V5, 5, SIMD_EMIT_SETTER },
+ { SN_set_V6, 6, SIMD_EMIT_SETTER },
+ { SN_set_V7, 7, SIMD_EMIT_SETTER },
+ { SN_set_V8, 8, SIMD_EMIT_SETTER },
+ { SN_set_V9, 9, SIMD_EMIT_SETTER },
+};
+
+/*
+Missing:
+setters
+ */
+static const SimdIntrinsc vector16sb_intrinsics[] = {
+ { SN_ctor, OP_EXPAND_I1, SIMD_EMIT_CTOR },
+ { SN_AddWithSaturation, OP_PADDB_SAT, SIMD_EMIT_BINARY },
+ { SN_CompareEqual, OP_PCMPEQB, SIMD_EMIT_BINARY },
+ { SN_CompareGreaterThan, OP_PCMPGTB, SIMD_EMIT_BINARY },
+ { SN_ExtractByteMask, 0, SIMD_EMIT_EXTRACT_MASK },
+ { SN_LoadAligned, 0, SIMD_EMIT_LOAD_ALIGNED },
+ { SN_Max, OP_PMAXB, SIMD_EMIT_BINARY, SIMD_VERSION_SSE41 },
+ { SN_Min, OP_PMINB, SIMD_EMIT_BINARY, SIMD_VERSION_SSE41 },
+ { SN_PrefetchTemporalAllCacheLevels, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_0 },
+ { SN_PrefetchTemporal1stLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_1 },
+ { SN_PrefetchTemporal2ndLevelCache, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_2 },
+ { SN_PrefetchNonTemporal, 0, SIMD_EMIT_PREFETCH, SIMD_VERSION_SSE1, SIMD_PREFETCH_MODE_NTA },
+ { SN_StoreAligned, OP_STOREX_ALIGNED_MEMBASE_REG, SIMD_EMIT_STORE },
+ { SN_SubtractWithSaturation, OP_PSUBB_SAT, SIMD_EMIT_BINARY },
+ { SN_UnpackHigh, OP_UNPACK_HIGHB, SIMD_EMIT_BINARY },
+ { SN_UnpackLow, OP_UNPACK_LOWB, SIMD_EMIT_BINARY },
+ { SN_get_V0, 0, SIMD_EMIT_GETTER },
+ { SN_get_V1, 1, SIMD_EMIT_GETTER },
+ { SN_get_V10, 10, SIMD_EMIT_GETTER },
+ { SN_get_V11, 11, SIMD_EMIT_GETTER },
+ { SN_get_V12, 12, SIMD_EMIT_GETTER },
+ { SN_get_V13, 13, SIMD_EMIT_GETTER },
+ { SN_get_V14, 14, SIMD_EMIT_GETTER },
+ { SN_get_V15, 15, SIMD_EMIT_GETTER },
+ { SN_get_V2, 2, SIMD_EMIT_GETTER },
+ { SN_get_V3, 3, SIMD_EMIT_GETTER },
+ { SN_get_V4, 4, SIMD_EMIT_GETTER },
+ { SN_get_V5, 5, SIMD_EMIT_GETTER },
+ { SN_get_V6, 6, SIMD_EMIT_GETTER },
+ { SN_get_V7, 7, SIMD_EMIT_GETTER },
+ { SN_get_V8, 8, SIMD_EMIT_GETTER },
+ { SN_get_V9, 9, SIMD_EMIT_GETTER },
+ { SN_op_Addition, OP_PADDB, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
+ { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+ { SN_op_Equality, OP_PCMPEQB, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
+ { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
+ { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+ { SN_op_Inequality, OP_PCMPEQB, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
+ { SN_op_Subtraction, OP_PSUBB, SIMD_EMIT_BINARY },
+ { SN_set_V0, 0, SIMD_EMIT_SETTER },
+ { SN_set_V1, 1, SIMD_EMIT_SETTER },
+ { SN_set_V10, 10, SIMD_EMIT_SETTER },
+ { SN_set_V11, 11, SIMD_EMIT_SETTER },
+ { SN_set_V12, 12, SIMD_EMIT_SETTER },
+ { SN_set_V13, 13, SIMD_EMIT_SETTER },
+ { SN_set_V14, 14, SIMD_EMIT_SETTER },
+ { SN_set_V15, 15, SIMD_EMIT_SETTER },
+ { SN_set_V2, 2, SIMD_EMIT_SETTER },
+ { SN_set_V3, 3, SIMD_EMIT_SETTER },
+ { SN_set_V4, 4, SIMD_EMIT_SETTER },
+ { SN_set_V5, 5, SIMD_EMIT_SETTER },
+ { SN_set_V6, 6, SIMD_EMIT_SETTER },
+ { SN_set_V7, 7, SIMD_EMIT_SETTER },
+ { SN_set_V8, 8, SIMD_EMIT_SETTER },
+ { SN_set_V9, 9, SIMD_EMIT_SETTER },
+};
+
+static guint32 simd_supported_versions;
+