+typedef enum {
+ INTRINS_MEMSET,
+ INTRINS_MEMCPY,
+ INTRINS_SADD_OVF_I32,
+ INTRINS_UADD_OVF_I32,
+ INTRINS_SSUB_OVF_I32,
+ INTRINS_USUB_OVF_I32,
+ INTRINS_SMUL_OVF_I32,
+ INTRINS_UMUL_OVF_I32,
+ INTRINS_SADD_OVF_I64,
+ INTRINS_UADD_OVF_I64,
+ INTRINS_SSUB_OVF_I64,
+ INTRINS_USUB_OVF_I64,
+ INTRINS_SMUL_OVF_I64,
+ INTRINS_UMUL_OVF_I64,
+ INTRINS_SIN,
+ INTRINS_COS,
+ INTRINS_SQRT,
+ INTRINS_FABS,
+ INTRINS_EXPECT_I8,
+ INTRINS_EXPECT_I1,
+#if defined(TARGET_AMD64) || defined(TARGET_X86)
+ INTRINS_SSE_PMOVMSKB,
+ INTRINS_SSE_PSRLI_W,
+ INTRINS_SSE_PSRAI_W,
+ INTRINS_SSE_PSLLI_W,
+ INTRINS_SSE_PSRLI_D,
+ INTRINS_SSE_PSRAI_D,
+ INTRINS_SSE_PSLLI_D,
+ INTRINS_SSE_PSRLI_Q,
+ INTRINS_SSE_PSLLI_Q,
+ INTRINS_SSE_SQRT_PD,
+ INTRINS_SSE_SQRT_PS,
+ INTRINS_SSE_RSQRT_PS,
+ INTRINS_SSE_RCP_PS,
+ INTRINS_SSE_CVTTPD2DQ,
+ INTRINS_SSE_CVTTPS2DQ,
+ INTRINS_SSE_CVTDQ2PD,
+ INTRINS_SSE_CVTDQ2PS,
+ INTRINS_SSE_CVTPD2DQ,
+ INTRINS_SSE_CVTPS2DQ,
+ INTRINS_SSE_CVTPD2PS,
+ INTRINS_SSE_CVTPS2PD,
+ INTRINS_SSE_CMPPD,
+ INTRINS_SSE_CMPPS,
+ INTRINS_SSE_PACKSSWB,
+ INTRINS_SSE_PACKUSWB,
+ INTRINS_SSE_PACKSSDW,
+ INTRINS_SSE_PACKUSDW,
+ INTRINS_SSE_MINPS,
+ INTRINS_SSE_MAXPS,
+ INTRINS_SSE_HADDPS,
+ INTRINS_SSE_HSUBPS,
+ INTRINS_SSE_ADDSUBPS,
+ INTRINS_SSE_MINPD,
+ INTRINS_SSE_MAXPD,
+ INTRINS_SSE_HADDPD,
+ INTRINS_SSE_HSUBPD,
+ INTRINS_SSE_ADDSUBPD,
+ INTRINS_SSE_PMINUD,
+ INTRINS_SSE_PMAXUD,
+ INTRINS_SSE_PMINUW,
+ INTRINS_SSE_PMINSW,
+ INTRINS_SSE_PMAXUW,
+ INTRINS_SSE_PADDSW,
+ INTRINS_SSE_PSUBSW,
+ INTRINS_SSE_PADDUSW,
+ INTRINS_SSE_PSUBUSW,
+ INTRINS_SSE_PAVGW,
+ INTRINS_SSE_PMULHW,
+ INTRINS_SSE_PMULHU,
+ INTRINS_SSE_PMINUB,
+ INTRINS_SSE_PMAXUB,
+ INTRINS_SE_PADDSB,
+ INTRINS_SSE_PSUBSB,
+ INTRINS_SSE_PADDUSB,
+ INTRINS_SSE_PSUBUSB,
+ INTRINS_SSE_PAVGB,
+ INTRINS_SSE_PAUSE,
+#endif
+ INTRINS_NUM
+} IntrinsicId;
+
+typedef struct {
+ IntrinsicId id;
+ const char *name;
+} IntrinsicDesc;
+
+static IntrinsicDesc intrinsics[] = {
+ {INTRINS_MEMSET, "llvm.memset.p0i8.i32"},
+ {INTRINS_MEMCPY, "llvm.memcpy.p0i8.p0i8.i32"},
+ {INTRINS_SADD_OVF_I32, "llvm.sadd.with.overflow.i32"},
+ {INTRINS_UADD_OVF_I32, "llvm.uadd.with.overflow.i32"},
+ {INTRINS_SSUB_OVF_I32, "llvm.ssub.with.overflow.i32"},
+ {INTRINS_USUB_OVF_I32, "llvm.usub.with.overflow.i32"},
+ {INTRINS_SMUL_OVF_I32, "llvm.smul.with.overflow.i32"},
+ {INTRINS_UMUL_OVF_I32, "llvm.umul.with.overflow.i32"},
+ {INTRINS_SADD_OVF_I64, "llvm.sadd.with.overflow.i64"},
+ {INTRINS_UADD_OVF_I64, "llvm.uadd.with.overflow.i64"},
+ {INTRINS_SSUB_OVF_I64, "llvm.ssub.with.overflow.i64"},
+ {INTRINS_USUB_OVF_I64, "llvm.usub.with.overflow.i64"},
+ {INTRINS_SMUL_OVF_I64, "llvm.smul.with.overflow.i64"},
+ {INTRINS_UMUL_OVF_I64, "llvm.umul.with.overflow.i64"},
+ {INTRINS_SIN, "llvm.sin.f64"},
+ {INTRINS_COS, "llvm.cos.f64"},
+ {INTRINS_SQRT, "llvm.sqrt.f64"},
+ /* This isn't an intrinsic, instead llvm seems to special case it by name */
+ {INTRINS_FABS, "fabs"},
+ {INTRINS_EXPECT_I8, "llvm.expect.i8"},
+ {INTRINS_EXPECT_I1, "llvm.expect.i1"},
+#if defined(TARGET_AMD64) || defined(TARGET_X86)
+ {INTRINS_SSE_PMOVMSKB, "llvm.x86.sse2.pmovmskb.128"},
+ {INTRINS_SSE_PSRLI_W, "llvm.x86.sse2.psrli.w"},
+ {INTRINS_SSE_PSRAI_W, "llvm.x86.sse2.psrai.w"},
+ {INTRINS_SSE_PSLLI_W, "llvm.x86.sse2.pslli.w"},
+ {INTRINS_SSE_PSRLI_D, "llvm.x86.sse2.psrli.d"},
+ {INTRINS_SSE_PSRAI_D, "llvm.x86.sse2.psrai.d"},
+ {INTRINS_SSE_PSLLI_D, "llvm.x86.sse2.pslli.d"},
+ {INTRINS_SSE_PSRLI_Q, "llvm.x86.sse2.psrli.q"},
+ {INTRINS_SSE_PSLLI_Q, "llvm.x86.sse2.pslli.q"},
+ {INTRINS_SSE_SQRT_PD, "llvm.x86.sse2.sqrt.pd"},
+ {INTRINS_SSE_SQRT_PS, "llvm.x86.sse.sqrt.ps"},
+ {INTRINS_SSE_RSQRT_PS, "llvm.x86.sse.rsqrt.ps"},
+ {INTRINS_SSE_RCP_PS, "llvm.x86.sse.rcp.ps"},
+ {INTRINS_SSE_CVTTPD2DQ, "llvm.x86.sse2.cvttpd2dq"},
+ {INTRINS_SSE_CVTTPS2DQ, "llvm.x86.sse2.cvttps2dq"},
+ {INTRINS_SSE_CVTDQ2PD, "llvm.x86.sse2.cvtdq2pd"},
+ {INTRINS_SSE_CVTDQ2PS, "llvm.x86.sse2.cvtdq2ps"},
+ {INTRINS_SSE_CVTPD2DQ, "llvm.x86.sse2.cvtpd2dq"},
+ {INTRINS_SSE_CVTPS2DQ, "llvm.x86.sse2.cvtps2dq"},
+ {INTRINS_SSE_CVTPD2PS, "llvm.x86.sse2.cvtpd2ps"},
+ {INTRINS_SSE_CVTPS2PD, "llvm.x86.sse2.cvtps2pd"},
+ {INTRINS_SSE_CMPPD, "llvm.x86.sse2.cmp.pd"},
+ {INTRINS_SSE_CMPPS, "llvm.x86.sse.cmp.ps"},
+ {INTRINS_SSE_PACKSSWB, "llvm.x86.sse2.packsswb.128"},
+ {INTRINS_SSE_PACKUSWB, "llvm.x86.sse2.packuswb.128"},
+ {INTRINS_SSE_PACKSSDW, "llvm.x86.sse2.packssdw.128"},
+ {INTRINS_SSE_PACKUSDW, "llvm.x86.sse41.packusdw"},
+ {INTRINS_SSE_MINPS, "llvm.x86.sse.min.ps"},
+ {INTRINS_SSE_MAXPS, "llvm.x86.sse.max.ps"},
+ {INTRINS_SSE_HADDPS, "llvm.x86.sse3.hadd.ps"},
+ {INTRINS_SSE_HSUBPS, "llvm.x86.sse3.hsub.ps"},
+ {INTRINS_SSE_ADDSUBPS, "llvm.x86.sse3.addsub.ps"},
+ {INTRINS_SSE_MINPD, "llvm.x86.sse2.min.pd"},
+ {INTRINS_SSE_MAXPD, "llvm.x86.sse2.max.pd"},
+ {INTRINS_SSE_HADDPD, "llvm.x86.sse3.hadd.pd"},
+ {INTRINS_SSE_HSUBPD, "llvm.x86.sse3.hsub.pd"},
+ {INTRINS_SSE_ADDSUBPD, "llvm.x86.sse3.addsub.pd"},
+ {INTRINS_SSE_PMINUD, "llvm.x86.sse41.pminud"},
+ {INTRINS_SSE_PMAXUD, "llvm.x86.sse41.pmaxud"},
+ {INTRINS_SSE_PMINUW, "llvm.x86.sse41.pminuw"},
+ {INTRINS_SSE_PMINSW, "llvm.x86.sse2.pmins.w"},
+ {INTRINS_SSE_PMAXUW, "llvm.x86.sse41.pmaxuw"},
+ {INTRINS_SSE_PADDSW, "llvm.x86.sse2.padds.w"},
+ {INTRINS_SSE_PSUBSW, "llvm.x86.sse2.psubs.w"},
+ {INTRINS_SSE_PADDUSW, "llvm.x86.sse2.paddus.w"},
+ {INTRINS_SSE_PSUBUSW, "llvm.x86.sse2.psubus.w"},
+ {INTRINS_SSE_PAVGW, "llvm.x86.sse2.pavg.w"},
+ {INTRINS_SSE_PMULHW, "llvm.x86.sse2.pmulh.w"},
+ {INTRINS_SSE_PMULHU, "llvm.x86.sse2.pmulhu.w"},
+ {INTRINS_SSE_PMINUB, "llvm.x86.sse2.pminu.b"},
+ {INTRINS_SSE_PMAXUB, "llvm.x86.sse2.pmaxu.b"},
+ {INTRINS_SE_PADDSB, "llvm.x86.sse2.padds.b"},
+ {INTRINS_SSE_PSUBSB, "llvm.x86.sse2.psubs.b"},
+ {INTRINS_SSE_PADDUSB, "llvm.x86.sse2.paddus.b"},
+ {INTRINS_SSE_PSUBUSB, "llvm.x86.sse2.psubus.b"},
+ {INTRINS_SSE_PAVGB, "llvm.x86.sse2.pavg.b"},
+ {INTRINS_SSE_PAUSE, "llvm.x86.sse2.pause"}
+#endif
+};
+