+ case OP_RCONV_TO_I1:
+ code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
+ break;
+ case OP_RCONV_TO_U1:
+ code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
+ break;
+ case OP_RCONV_TO_I2:
+ code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
+ break;
+ case OP_RCONV_TO_U2:
+ code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
+ break;
+ case OP_RCONV_TO_I4:
+ code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
+ break;
+ case OP_RCONV_TO_U4:
+ code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
+ break;
+ case OP_RCONV_TO_R4:
+ g_assert (IS_VFP);
+ if (ins->dreg != ins->sreg1)
+ ARM_CPYS (code, ins->dreg, ins->sreg1);
+ break;
+ case OP_RCONV_TO_R8:
+ g_assert (IS_VFP);
+ ARM_CVTS (code, ins->dreg, ins->sreg1);
+ break;
+ case OP_RADD:
+ ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
+ break;
+ case OP_RSUB:
+ ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
+ break;
+ case OP_RMUL:
+ ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
+ break;
+ case OP_RDIV:
+ ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
+ break;
+ case OP_RNEG:
+ ARM_NEGS (code, ins->dreg, ins->sreg1);
+ break;
+ case OP_RCEQ:
+ if (IS_VFP) {
+ ARM_CMPS (code, ins->sreg1, ins->sreg2);
+ ARM_FMSTAT (code);
+ }
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
+ break;
+ case OP_RCLT:
+ if (IS_VFP) {
+ ARM_CMPS (code, ins->sreg1, ins->sreg2);
+ ARM_FMSTAT (code);
+ }
+ ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
+ break;
+ case OP_RCLT_UN:
+ if (IS_VFP) {
+ ARM_CMPS (code, ins->sreg1, ins->sreg2);
+ ARM_FMSTAT (code);
+ }
+ ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
+ break;
+ case OP_RCGT:
+ if (IS_VFP) {
+ ARM_CMPS (code, ins->sreg2, ins->sreg1);
+ ARM_FMSTAT (code);
+ }
+ ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
+ break;
+ case OP_RCGT_UN:
+ if (IS_VFP) {
+ ARM_CMPS (code, ins->sreg2, ins->sreg1);
+ ARM_FMSTAT (code);
+ }
+ ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
+ break;
+ case OP_RCNEQ:
+ if (IS_VFP) {
+ ARM_CMPS (code, ins->sreg1, ins->sreg2);
+ ARM_FMSTAT (code);
+ }
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
+ break;
+ case OP_RCGE:
+ if (IS_VFP) {
+ ARM_CMPS (code, ins->sreg1, ins->sreg2);
+ ARM_FMSTAT (code);
+ }
+ ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
+ break;
+ case OP_RCLE:
+ if (IS_VFP) {
+ ARM_CMPS (code, ins->sreg2, ins->sreg1);
+ ARM_FMSTAT (code);
+ }
+ ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
+ ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
+ break;
+