+#elif defined(ARM_FPU_VFP)
+ case OP_R8CONST:
+ /* FIXME: we can optimize the imm load by dealing with part of
+ * the displacement in LDFD (aligning to 512).
+ */
+ code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
+ ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
+ break;
+ case OP_R4CONST:
+ code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
+ ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
+ ARM_CVTS (code, ins->dreg, ins->dreg);
+ break;
+ case OP_STORER8_MEMBASE_REG:
+ g_assert (arm_is_fpimm8 (ins->inst_offset));
+ ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
+ break;
+ case OP_LOADR8_MEMBASE:
+ g_assert (arm_is_fpimm8 (ins->inst_offset));
+ ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
+ break;
+ case OP_STORER4_MEMBASE_REG:
+ g_assert (arm_is_fpimm8 (ins->inst_offset));
+ ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
+ break;
+ case OP_LOADR4_MEMBASE:
+ g_assert (arm_is_fpimm8 (ins->inst_offset));
+ ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
+ break;
+ case CEE_CONV_R_UN: {