- for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
- amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
- amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
- }
+ /* rax/rcx/rdx/r8/r9 is scratch */
+ limit_reg = AMD64_RAX;
+ index_reg = AMD64_RCX;
+ src_reg = AMD64_R8;
+ dst_reg = AMD64_R9;
+ amd64_mov_reg_membase (code, limit_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
+ amd64_mov_reg_imm (code, index_reg, 0);
+ amd64_lea_membase (code, src_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS) * sizeof(mgreg_t)));
+ amd64_mov_reg_reg (code, dst_reg, AMD64_RSP, 8);
+ buf [0] = code;
+ x86_jump8 (code, 0);
+ buf [1] = code;
+ amd64_mov_reg_membase (code, AMD64_RDX, src_reg, 0, 8);
+ amd64_mov_membase_reg (code, dst_reg, 0, AMD64_RDX, 8);
+ amd64_alu_reg_imm (code, X86_ADD, index_reg, 1);
+ amd64_alu_reg_imm (code, X86_ADD, src_reg, 8);
+ amd64_alu_reg_imm (code, X86_ADD, dst_reg, 8);
+ amd64_patch (buf [0], code);
+ amd64_alu_reg_reg (code, X86_CMP, index_reg, limit_reg);
+ buf [2] = code;
+ x86_branch8 (code, X86_CC_LT, 0, FALSE);
+ amd64_patch (buf [2], buf [1]);