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2008-04-08 Zoltan Varga <vargaz@gmail.com>
[mono.git]
/
mono
/
mini
/
inssel-amd64.brg
diff --git
a/mono/mini/inssel-amd64.brg
b/mono/mini/inssel-amd64.brg
index 327d3b50db95b25154b4912b7fa3cef03cc83009..cae37504357d77d5649a437a1fe4f8a195c377cc 100644
(file)
--- a/
mono/mini/inssel-amd64.brg
+++ b/
mono/mini/inssel-amd64.brg
@@
-49,26
+49,31
@@
# (C) 2002 Ximian, Inc.
#
# (C) 2002 Ximian, Inc.
#
-stmt: OP_START_HANDLER {
- MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
- MONO_EMIT_NEW_STORE_MEMBASE (s, OP_STORE_MEMBASE_REG, spvar->inst_basereg, spvar->inst_offset, X86_ESP);
+reg: CEE_LDIND_I8 (OP_REGVAR) {
+ state->reg1 = state->left->tree->dreg;
+}
+
+stmt: CEE_STIND_I8 (OP_REGVAR, reg) {
+ MONO_EMIT_NEW_UNALU (s, OP_MOVE, state->left->tree->dreg, state->right->reg1);
}
}
-stmt: CEE_ENDFINALLY {
- MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
- MONO_EMIT_NEW_LOAD_MEMBASE (s, X86_ESP, spvar->inst_basereg, spvar->inst_offset);
- tree->opcode = CEE_RET;
+reg: CEE_LDIND_I1 (OP_REGVAR) {
+ MONO_EMIT_UNALU (s, tree, OP_SEXT_I1, state->reg1, state->left->tree->dreg);}
+
+reg: CEE_LDIND_I2 (OP_REGVAR) {
+ MONO_EMIT_UNALU (s, tree, OP_SEXT_I2, state->reg1, state->left->tree->dreg);}
+
+stmt: OP_START_HANDLER,
+stmt: OP_ENDFINALLY {
mono_bblock_add_inst (s->cbb, tree);
}
stmt: OP_ENDFILTER (reg) {
mono_bblock_add_inst (s->cbb, tree);
}
stmt: OP_ENDFILTER (reg) {
- MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
- MONO_EMIT_NEW_UNALU (s, OP_MOVE, X86_EAX, state->left->reg1);
- MONO_EMIT_NEW_LOAD_MEMBASE (s, X86_ESP, spvar->inst_basereg, spvar->inst_offset);
- tree->opcode = CEE_RET;
+ tree->sreg1 = state->left->reg1;
mono_bblock_add_inst (s->cbb, tree);
}
mono_bblock_add_inst (s->cbb, tree);
}
+freg: OP_LCONV_TO_R_UN (reg),
freg: OP_LCONV_TO_R8 (reg) {
tree->sreg1 = state->left->reg1;
tree->dreg = state->reg1;
freg: OP_LCONV_TO_R8 (reg) {
tree->sreg1 = state->left->reg1;
tree->dreg = state->reg1;
@@
-121,7
+126,7
@@
reg: OP_LOCALLOC (OP_ICONST) {
mono_bblock_add_inst (s->cbb, tree);
} else {
guint32 size = state->left->tree->inst_c0;
mono_bblock_add_inst (s->cbb, tree);
} else {
guint32 size = state->left->tree->inst_c0;
- size = (size + (MONO_ARCH_
FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME
_ALIGNMENT - 1);
+ size = (size + (MONO_ARCH_
LOCALLOC_ALIGNMENT - 1)) & ~ (MONO_ARCH_LOCALLOC
_ALIGNMENT - 1);
MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, size);
MONO_EMIT_UNALU (s, tree, OP_MOVE, state->reg1, X86_ESP);
}
MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, size);
MONO_EMIT_UNALU (s, tree, OP_MOVE, state->reg1, X86_ESP);
}
@@
-350,6
+355,10
@@
stmt: OP_AMD64_OUTARG_ALIGN_STACK {
MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
}
MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
}
+stmt: OP_AMD64_SAVE_SP_TO_LMF {
+ mono_bblock_add_inst (s->cbb, tree);
+}
+
base: OP_INARG_VT (base) {
MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->tree->inst_basereg,
state->left->tree->inst_offset);
base: OP_INARG_VT (base) {
MONO_EMIT_NEW_LOAD_MEMBASE (s, state->reg1, state->left->tree->inst_basereg,
state->left->tree->inst_offset);
@@
-597,19
+606,19
@@
freg: OP_FCONV_TO_R4 (freg) "0" {
reg: CEE_ADD(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
reg: CEE_ADD(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_
REG_
MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: CEE_SUB(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
}
reg: CEE_SUB(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_
REG_
MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: CEE_MUL(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
}
reg: CEE_MUL(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_
REG_
MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: OP_LSHL (reg, reg),
}
reg: OP_LSHL (reg, reg),
@@
-621,7
+630,11
@@
reg: OP_LDIV_UN (reg, reg),
reg: OP_LREM (reg, reg),
reg: OP_LREM_UN (reg, reg),
reg: OP_LMUL_OVF (reg, reg),
reg: OP_LREM (reg, reg),
reg: OP_LREM_UN (reg, reg),
reg: OP_LMUL_OVF (reg, reg),
-reg: OP_LMUL_OVF_UN (reg, reg) "0" {
+reg: OP_LMUL_OVF_UN (reg, reg),
+reg: OP_IMIN (reg, reg),
+reg: OP_IMAX (reg, reg),
+reg: OP_LMIN (reg, reg),
+reg: OP_LMAX (reg, reg) "0" {
MONO_EMIT_BIALU (s, tree, tree->opcode, state->reg1, state->left->reg1, state->right->reg1);
}
MONO_EMIT_BIALU (s, tree, tree->opcode, state->reg1, state->left->reg1, state->right->reg1);
}
@@
-651,7
+664,6
@@
reg: OP_ATOMIC_EXCHANGE_I8 (base, reg) {
}
# Optimized call instructions
}
# Optimized call instructions
-# mono_arch_patch_delegate_trampoline depends on these
reg: OP_CALL_REG (CEE_LDIND_I (base)),
freg: OP_FCALL_REG (CEE_LDIND_I (base)),
reg: OP_LCALL_REG (CEE_LDIND_I (base)) {
reg: OP_CALL_REG (CEE_LDIND_I (base)),
freg: OP_FCALL_REG (CEE_LDIND_I (base)),
reg: OP_LCALL_REG (CEE_LDIND_I (base)) {