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[wasm] Add one more wasm_invoke entry.
[mono.git]
/
mono
/
mini
/
cpu-arm.md
diff --git
a/mono/mini/cpu-arm.md
b/mono/mini/cpu-arm.md
index 49bc57e72e84fd45a78bfde7aac37ac59a1d9e87..e6a91fc176d13fc9474efdeb53841cdfb7097ec4 100644
(file)
--- a/
mono/mini/cpu-arm.md
+++ b/
mono/mini/cpu-arm.md
@@
-1,5
+1,6
@@
# Copyright 2003-2011 Novell, Inc (http://www.novell.com)
# Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
# Copyright 2003-2011 Novell, Inc (http://www.novell.com)
# Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
+# Licensed under the MIT license. See LICENSE file in the project root for full license information.
# arm cpu description file
# this file is read by genmdesc to pruduce a table with all the relevant information
# about the cpu instructions that may be used by the regsiter allocator, the scheduler
# arm cpu description file
# this file is read by genmdesc to pruduce a table with all the relevant information
# about the cpu instructions that may be used by the regsiter allocator, the scheduler
@@
-82,22
+83,22
@@
setlret: src1:i src2:i len:12
checkthis: src1:b len:4
call: dest:a clob:c len:20
call_reg: dest:a src1:i len:8 clob:c
checkthis: src1:b len:4
call: dest:a clob:c len:20
call_reg: dest:a src1:i len:8 clob:c
-call_membase: dest:a src1:b len:
24
clob:c
+call_membase: dest:a src1:b len:
30
clob:c
voidcall: len:20 clob:c
voidcall_reg: src1:i len:8 clob:c
voidcall: len:20 clob:c
voidcall_reg: src1:i len:8 clob:c
-voidcall_membase: src1:b len:
16
clob:c
+voidcall_membase: src1:b len:
24
clob:c
fcall: dest:g len:28 clob:c
fcall_reg: dest:g src1:i len:16 clob:c
fcall: dest:g len:28 clob:c
fcall_reg: dest:g src1:i len:16 clob:c
-fcall_membase: dest:g src1:b len:
24
clob:c
+fcall_membase: dest:g src1:b len:
30
clob:c
rcall: dest:g len:28 clob:c
rcall_reg: dest:g src1:i len:16 clob:c
rcall: dest:g len:28 clob:c
rcall_reg: dest:g src1:i len:16 clob:c
-rcall_membase: dest:g src1:b len:
24
clob:c
+rcall_membase: dest:g src1:b len:
30
clob:c
lcall: dest:l len:20 clob:c
lcall_reg: dest:l src1:i len:8 clob:c
lcall: dest:l len:20 clob:c
lcall_reg: dest:l src1:i len:8 clob:c
-lcall_membase: dest:l src1:b len:
16
clob:c
+lcall_membase: dest:l src1:b len:
24
clob:c
vcall: len:64 clob:c
vcall_reg: src1:i len:64 clob:c
vcall: len:64 clob:c
vcall_reg: src1:i len:64 clob:c
-vcall_membase: src1:b len:
64
clob:c
+vcall_membase: src1:b len:
70
clob:c
tailcall: len:160 clob:c
iconst: dest:i len:16
r4const: dest:f len:24
tailcall: len:160 clob:c
iconst: dest:i len:16
r4const: dest:f len:24
@@
-243,10
+244,8
@@
sbb_imm: dest:i src1:i len:12
br_reg: src1:i len:8
bigmul: len:8 dest:l src1:i src2:i
bigmul_un: len:8 dest:l src1:i src2:i
br_reg: src1:i len:8
bigmul: len:8 dest:l src1:i src2:i
bigmul_un: len:8 dest:l src1:i src2:i
-tls_get: len:24 dest:i clob:c
-tls_get_reg: len:28 dest:i src1:i clob:c
-tls_set: len:24 src1:i clob:c
-tls_set_reg: len:28 src1:i src2:i clob:c
+tls_get: len:16 dest:i
+tls_set: len:16 src1:i clob:c
# 32 bit opcodes
int_add: dest:i src1:i src2:i len:4
# 32 bit opcodes
int_add: dest:i src1:i src2:i len:4
@@
-361,7
+360,7
@@
long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
vcall2: len:64 clob:c
vcall2_reg: src1:i len:64 clob:c
vcall2_membase: src1:b len:64 clob:c
vcall2: len:64 clob:c
vcall2_reg: src1:i len:64 clob:c
vcall2_membase: src1:b len:64 clob:c
-dyn_call: src1:i src2:i len:
136
clob:c
+dyn_call: src1:i src2:i len:
252
clob:c
# This is different from the original JIT opcodes
float_beq: len:32
# This is different from the original JIT opcodes
float_beq: len:32
@@
-405,3
+404,5
@@
atomic_store_r4: dest:b src1:f len:80
atomic_store_r8: dest:b src1:f len:32
generic_class_init: src1:a len:44 clob:c
atomic_store_r8: dest:b src1:f len:32
generic_class_init: src1:a len:44 clob:c
+
+fill_prof_call_ctx: src1:i len:128