+#if SIZEOF_REGISTER == 4
+
+#define MIPS_SW mips_sw
+#define MIPS_LW mips_lw
+#define MIPS_ADDU mips_addu
+#define MIPS_ADDIU mips_addiu
+#define MIPS_SWC1 mips_swc1
+#define MIPS_LWC1 mips_lwc1
+#define MIPS_MOVE mips_move
+
+#elif SIZEOF_REGISTER == 8
+
+#define MIPS_SW mips_sd
+#define MIPS_LW mips_ld
+#define MIPS_ADDU mips_daddu
+#define MIPS_ADDIU mips_daddiu
+#define MIPS_SWC1 mips_sdc1
+#define MIPS_LWC1 mips_ldc1
+#define MIPS_MOVE mips_dmove
+
+#else
+#error Unknown SIZEOF_REGISTER
+#endif
+
+#define mips_emit32(c,x) do { \
+ *((guint32 *) (void *)(c)) = x; \
+ (c) = (typeof(c))(((guint32 *)(void *)(c)) + 1); \
+ } while (0)
+
+#define mips_format_i(code,op,rs,rt,imm) mips_emit32 ((code), (((op)<<26)|((rs)<<21)|((rt)<<16)|((imm)&0xffff)))
+#define mips_format_j(code,op,imm) mips_emit32 ((code), (((op)<<26)|((imm)&0x03ffffff)))
+#define mips_format_r(code,op,rs,rt,rd,sa,func) mips_emit32 ((code), (((op)<<26)|((rs)<<21)|((rt)<<16)|((rd)<<11)|((sa)<<6)|(func)))
+#define mips_format_divmul(code,op,src1,src2,fun) mips_emit32 ((code), (((op)<<26)|((src1)<<21)|((src2)<<16)|(fun)))
+
+#define mips_is_imm16(val) ((gint)(gshort)(gint)(val) == (gint)(val))
+
+/* Load always using lui/addiu pair (for later patching) */
+#define mips_load(c,D,v) do { \
+ if (((guint32)(v)) & (1 << 15)) { \
+ mips_lui ((c), (D), mips_zero, (((guint32)(v))>>16)+1); \
+ } \
+ else { \
+ mips_lui ((c), (D), mips_zero, (((guint32)(v))>>16)); \
+ } \
+ mips_addiu ((c), (D), (D), ((guint32)(v)) & 0xffff); \
+ } while (0)
+
+/* load constant - no patch-up */
+#define mips_load_const(c,D,v) do { \
+ if (!mips_is_imm16 ((v))) { \
+ if (((guint32)(v)) & (1 << 15)) { \
+ mips_lui ((c), (D), mips_zero, (((guint32)(v))>>16)+1); \
+ } \
+ else { \
+ mips_lui ((c), (D), mips_zero, (((guint32)(v))>>16)); \
+ } \
+ if (((guint32)(v)) & 0xffff) \
+ mips_addiu ((c), (D), (D), ((guint32)(v)) & 0xffff); \
+ } \
+ else \
+ mips_addiu ((c), (D), mips_zero, ((guint32)(v)) & 0xffff); \
+ } while (0)
+