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bootrom: removed 'ABC' output on UART
[calu.git]
/
cpu
/
src
/
decode_stage_b.vhd
diff --git
a/cpu/src/decode_stage_b.vhd
b/cpu/src/decode_stage_b.vhd
index 92c0f7186d645f4b47b6a9f929fe3f2482f663b7..e57460946e55d1213020a75dbcd5fb8234011ed3 100644
(file)
--- a/
cpu/src/decode_stage_b.vhd
+++ b/
cpu/src/decode_stage_b.vhd
@@
-67,6
+67,7
@@
begin
dec_op_inst.saddr2 <= (others => '0');
dec_op_inst.daddr <= (others => '0');
dec_op_inst.displacement <= (others => '0');
dec_op_inst.saddr2 <= (others => '0');
dec_op_inst.daddr <= (others => '0');
dec_op_inst.displacement <= (others => '0');
+ dec_op_inst.prog_cnt <= (others => '0');
elsif rising_edge(clk) then
rtw_rec <= rtw_rec_nxt;
elsif rising_edge(clk) then
rtw_rec <= rtw_rec_nxt;
@@
-92,7
+93,7
@@
end process;
-- end record;
-- output logic incl. bypassing reg-file
-- end record;
-- output logic incl. bypassing reg-file
-output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
+output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data
, nop
)
begin
begin
@@
-100,11
+101,15
@@
begin
to_next_stage.src1 <= reg1_rd_data;
to_next_stage.src2 <= reg2_rd_data;
to_next_stage.src1 <= reg1_rd_data;
to_next_stage.src2 <= reg2_rd_data;
+ if (nop = '1') then
+ to_next_stage.condition <= "1111";
+ end if;
+
end process;
-- fills output register
end process;
-- fills output register
-to_next: process(instr_spl)
+to_next: process(instr_spl
, prog_cnt
)
begin
dec_op_inst_nxt.condition <= instr_spl.predicates;
begin
dec_op_inst_nxt.condition <= instr_spl.predicates;
@@
-117,6
+122,7
@@
begin
dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
dec_op_inst_nxt.op_group <= instr_spl.op_group;
dec_op_inst_nxt.displacement <= instr_spl.displacement;
dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
dec_op_inst_nxt.op_group <= instr_spl.op_group;
dec_op_inst_nxt.displacement <= instr_spl.displacement;
+ dec_op_inst_nxt.prog_cnt <= prog_cnt;
end process;
end process;
@@
-157,7
+163,7
@@
begin
rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
- if (instr_spl.op_detail(IMM_OPT) = '1') then
+ if (instr_spl.op_detail(IMM_OPT) = '1') then
-- or instr_spl.op_group = LDST_OP
rtw_rec_nxt.immediate <= instr_spl.immediate;
rtw_rec_nxt.imm_set <= '1';
end if;
rtw_rec_nxt.immediate <= instr_spl.immediate;
rtw_rec_nxt.imm_set <= '1';
end if;
@@
-174,7
+180,7
@@
end process;
-- async process: calculates branch prediction
-- async process: calculates branch prediction
-br_pred: process(instr_spl)
+br_pred: process(instr_spl
, prog_cnt, reset
)
begin
begin
@@
-182,10
+188,18
@@
begin
branch_prediction_bit <= '0';
if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
branch_prediction_bit <= '0';
if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
- branch_prediction_res <= instr_spl.immediate; --both 32 bit
+ if instr_spl.int = '0' then
+ branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit
+ else
+ branch_prediction_res <= instr_spl.immediate;
+ end if;
branch_prediction_bit <= '1';
end if;
branch_prediction_bit <= '1';
end if;
+ if reset = RESET_VALUE then
+ branch_prediction_bit <= '0';
+ end if;
+
end process;
end behav;
end process;
end behav;