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cyclone: pinmapping und reset angepasst
[calu.git]
/
cpu
/
src
/
core_top.vhd
diff --git
a/cpu/src/core_top.vhd
b/cpu/src/core_top.vhd
index 242683e1ec73ca22cfcfd6c4477269b185a1965d..13d826353a37e25de0c3d57c7922b4984fd80bee 100644
(file)
--- a/
cpu/src/core_top.vhd
+++ b/
cpu/src/core_top.vhd
@@
-17,6
+17,7
@@
entity core_top is
-- uart
bus_tx : out std_logic;
bus_rx : in std_logic;
-- uart
bus_tx : out std_logic;
bus_rx : in std_logic;
+ led2 : out std_logic;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
@@
-98,7
+99,8
@@
begin
im_data => im_data,
--Data outputs
instruction => instruction_pin, --: out instruction_word_t
im_data => im_data,
--Data outputs
instruction => instruction_pin, --: out instruction_word_t
- prog_cnt => prog_cnt_pin
+ prog_cnt => prog_cnt_pin,
+ led2 => led2
);
decode_st : decode_stage
);
decode_st : decode_stage
@@
-167,7
+169,7
@@
syn: process(sys_clk, sys_res)
begin
begin
- if sys_res = '
0
' then
+ if sys_res = '
1
' then
-- vers.result <= (others => '0');
-- vers.result_addr <= (others => '0');
-- vers.address <= (others => '0');
-- vers.result <= (others => '0');
-- vers.result_addr <= (others => '0');
-- vers.address <= (others => '0');
@@
-184,7
+186,7
@@
begin
elsif rising_edge(sys_clk) then
-- vers <= vers_nxt;
elsif rising_edge(sys_clk) then
-- vers <= vers_nxt;
- sync(1) <= sys_res;
+ sync(1) <=
not
sys_res;
for i in 2 to SYNC_STAGES loop
sync(i) <= sync(i - 1);
end loop;
for i in 2 to SYNC_STAGES loop
sync(i) <= sync(i - 1);
end loop;