+ type instruction_rec is record
+
+ predicates : std_logic_vector(3 downto 0);
+
+ opcode : opcode_t;
+
+ reg_dest_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+ reg_src1_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+ reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+
+ immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
+
+ displacement : gp_register_t;
+
+ jmptype : std_logic_vector(1 downto 0);
+
+ high_low, fill, signext, bp: std_logic;
+
+ op_detail : op_opt_t;
+ op_group : op_info_t;
+
+ end record;
+
+
+ type read_through_write_rec is record
+
+ rtw_reg : gp_register_t;
+ rtw_reg1 : std_logic;
+ rtw_reg2 : std_logic;
+ immediate : gp_register_t;
+ imm_set : std_logic;
+ reg1_addr : gp_addr_t;
+ reg2_addr : gp_addr_t;
+
+ end record;
+
+ type dec_op is record