- signal left, right : gp_register_t;\r
- \r
-begin\r
-\r
- add_inst : entity work.exec_op(add_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, add_result);\r
- \r
- and_inst : entity work.exec_op(and_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, and_result);\r
-\r
- or_inst : entity work.exec_op(or_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, or_result);\r
-\r
- xor_inst : entity work.exec_op(xor_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, xor_result);\r
- \r
- shift_inst : entity work.exec_op(shift_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
-\r
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
- variable result_v : alu_result_rec;\r
- variable res_prod : std_logic;\r
- variable cond_met : std_logic;\r
+ signal left_o, right_o : gp_register_t;
+
+begin
+
+ add_inst : entity work.exec_op(add_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);
+
+ and_inst : entity work.exec_op(and_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);
+
+ or_inst : entity work.exec_op(or_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);
+
+ xor_inst : entity work.exec_op(xor_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);
+
+ shift_inst : entity work.exec_op(shift_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);
+
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval, pval_nxt)
+ variable result_v : alu_result_rec;
+ variable res_prod : std_logic;
+ variable cond_met : std_logic;