uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET uses HAVE_OPTION_TABLE uses USE_OPTION_TABLE uses CONFIG_ROM_STREAM uses IRQ_SLOT_COUNT uses MAINBOARD uses ARCH uses FALLBACK_SIZE uses STACK_SIZE uses HEAP_SIZE uses ROM_SIZE uses ROM_SECTION_SIZE uses ROM_IMAGE_SIZE uses ROM_SECTION_SIZE uses ROM_SECTION_OFFSET uses CONFIG_ROM_STREAM_START uses PAYLOAD_SIZE uses _ROMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE uses HAVE_MP_TABLE uses HAVE_ACPI_TABLES ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 ### ### Build options ### ## ## Build code for the fallback boot ## default HAVE_FALLBACK_BOOT=1 ## ## no MP table ## default HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from linuxBIOS ## default HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 default IRQ_SLOT_COUNT=5 object irq_tables.o ## ## Build code to export a CMOS option table ## default HAVE_OPTION_TABLE=1 ### ### LinuxBIOS layout values ### ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. default ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## default STACK_SIZE=0x2000 ## ## Use a small 16K heap ## default HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE default USE_OPTION_TABLE = 0 ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) default ROM_SECTION_OFFSET = 0 end ## ## Compute the start location and size size of ## The linuxBIOS bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_STREAM = 1 ## ## Compute where this copy of linuxBIOS will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up linuxBIOS, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture ## arch i386 end ## ## Build the objects we have code for in this directory. ## driver mainboard.o #object reset.o if HAVE_ACPI_TABLES object fadt.o object dsdt.o end ## ## Romcc output ## makerule ./failover.E depends "$(MAINBOARD)/failover.c" action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" end makerule ./failover.inc depends "./failover.E ./romcc" action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E" end makerule ./auto.E depends "$(MAINBOARD)/auto.c" action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" end makerule ./auto.inc depends "./auto.E ./romcc" action "./romcc -O -mcpu=c3 ./auto.E " end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry32.inc ldscript /cpu/i386/entry16.lds ldscript /cpu/i386/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/i386/reset16.inc ldscript /cpu/i386/reset16.lds else mainboardinit cpu/i386/reset32.inc ldscript /cpu/i386/reset32.lds end ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds ## ## Setup our mtrrs ## # mainboardinit cpu/p6/earlymtrr.inc ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end ### ### O.k. We aren't just an intermediary anymore! ### ## ## Setup RAM ## mainboardinit ./auto.inc ## ## Include the secondary Configuration files ## dir /pc80 config chip.h northbridge via/vt8623 "vt8623" southbridge via/vt8235 "vt8235" register "enable_usb" = "0" register "enable_native_ide" = "0" register "enable_com_ports" = "1" register "enable_keyboard" = "0" register "enable_nvram" = "1" end southbridge ricoh/rl5c476 "rl5c476" end superio via/vt1211 "vt1211" register "enable_com_ports" = "1" register "enable_hwmon" = "1" register "enable_lpt" = "1" register "enable_fdc" = "1" end end cpu p6 "cpu0" end ## ## Include the old serial code for those few places that still need it. ## mainboardinit pc80/serial.inc mainboardinit arch/i386/lib/console.inc