/* * This file is part of the coreboot project. * * Copyright (C) 2007 AMD * Written by Yinghai Lu for AMD. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif #include #include #include #include #include #include #include #include #include #include #include #include #include // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ } static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } #include "northbridge/amd/amdk8/amdk8_f.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { uint32_t dword; uint8_t byte; enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // Node 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); /* Setup the mcp55 */ mcp55_enable_rom(); } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); uart_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_mb_resource_map(); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } #endif init_timer(); // Need to use TMICT to synconize FID/VID needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); // enable_smbus(); /* enable in sio_setup */ /* all ap stopped? */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }