## ## This file is part of the coreboot project. ## ## Copyright (C) 2010 Marc Bertens ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## chip northbridge/intel/i440bx # Northbridge device lapic_cluster 0 on # (L)APIC cluster chip cpu/intel/socket_PGA370 # CPU socket device lapic 0 on end # Local APIC of the CPU end end device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci f.0 on chip southbridge/ti/pci1x2x device pci 00.0 on end register "cltr" = "0x40" register "bcr" = "0x7c0" register "scr" = "0x08449060" register "mrr" = "0x00007522" end end device pci 7.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) device pnp 3f0.0 off end # Floppy (No connector) device pnp 3f0.3 off end # Parallel port (No connector) device pnp 3f0.4 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 3f0.5 on # COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 3f0.6 on # RTC irq 0x63 = 0x72 end device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector) end device pnp 3f0.8 on # AUX I/O irq 0x24 = 0x84 # OSC irq 0xB2 = 0x0C # Soft power status 1 irq 0xB3 = 0x05 # Soft power status 2 irq 0xC0 = 0x03 # IRQ MUX control irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable irq 0xCA = 0x09 # GP52 = IRQ8 (output) irq 0xCB = 0x01 # GP53 = nROMCS (output) irq 0xCC = 0x11 # GP54 = (I/O) input irq 0xF9 = 0x00 # read/write GP5x lines (0x1C) irq 0xD0 = 0x08 # GP60 = IRQ1 irq 0xD1 = 0x08 # GP61 = IRQ3 irq 0xD2 = 0x08 # GP62 = IRQ4 irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board irq 0xD4 = 0x11 # GP64 = (I/O) input irq 0xD5 = 0x11 # GP65 = (I/O) input irq 0xD6 = 0x08 # GP66 = IRQ8 irq 0xD7 = 0x11 # GP67 = (I/O) input irq 0xFA = 0x00 # read/write GP6x lines (0x88) irq 0xE0 = 0x00 # GP10 (I/O) = output irq 0xE1 = 0x01 # GP11 (I/O) = input irq 0xE2 = 0x08 # GP12 = P17 irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low irq 0xE4 = 0x00 # GP14 (I/O) = output irq 0xE5 = 0x00 # GP15 (I/O) = output irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low irq 0xF6 = 0xFF # read/write GP1x lines (0xCA) irq 0xEF = 0x00 # GP_INT2 disable irq 0xF0 = 0x00 # GP_INT1 disable irq 0xF1 = 0x00 # WDT_UNITS irq 0xF2 = 0x00 # WDT_VAL irq 0xF3 = 0x00 # WDT_CFG irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt) end device pnp 3f0.a off # ACPI (No support yet) # irq 0x60 = 0x0C # irq 0x61 = 0x80 end end end device pci 7.1 on end # IDE device pci 7.2 off end # USB (No connector) device pci 7.3 off end # ACPI (No support yet) register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" # Disable UDMA/33 for lower speed if your IDE device(s) don't support it. register "ide0_drive0_udma33_enable" = "1" register "ide0_drive1_udma33_enable" = "1" register "ide1_drive0_udma33_enable" = "1" register "ide1_drive1_udma33_enable" = "1" end end end