##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

chip northbridge/intel/i440bx		# Northbridge
  device lapic_cluster 0 on		# (L)APIC cluster
    chip cpu/intel/socket_PGA370	# CPU socket
      device lapic 0 on end		# Local APIC of the CPU
    end
  end
  device pci_domain 0 on		# PCI domain
    device pci 0.0 on end		# Host bridge
    device pci 1.0 on end		# PCI/AGP bridge
    chip southbridge/intel/i82371eb	# Southbridge
      device pci 7.0 on			# ISA bridge
        chip superio/smsc/smscsuperio	# Super I/O (SMSC FDC37B787)
          device pnp 3f0.0 off end	# Floppy (No connector)
          device pnp 3f0.3 off end	# Parallel port (No connector)
          device pnp 3f0.4 on		# COM1
            io 0x60 = 0x3f8
            irq 0x70 = 4
          end
          device pnp 3f0.5 on		# COM2 / IR
            io 0x60 = 0x2f8
            irq 0x70 = 3
          end
          device pnp 3f0.6 on end	# RTC
          device pnp 3f0.7 off end	# PS/2 keyboard / mouse (No connector)
          device pnp 3f0.8 on end	# AUX I/O
          device pnp 3f0.a off end	# ACPI (No support yet)
        end
      end
      device pci 7.1 on end		# IDE
      device pci 7.2 off end		# USB (No connector)
      device pci 7.3 off end		# ACPI (No support yet)
      register "ide0_enable" = "1"
      register "ide1_enable" = "1"
      register "ide_legacy_enable" = "1"
      # Disable UDMA/33 for lower speed if your IDE device(s) don't support it.
      register "ide0_drive0_udma33_enable" = "1"
      register "ide0_drive1_udma33_enable" = "1"
      register "ide1_drive0_udma33_enable" = "1"
      register "ide1_drive1_udma33_enable" = "1"
    end
  end
end