## ## This file is part of the coreboot project. ## ## Copyright (C) 2007 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit ./auto.inc mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) device apic 0 on end # APIC end end device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge chip superio/ite/it8671f # Super I/O device pnp 3f0.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 3f0.1 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 3f0.2 on # COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 3f0.3 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 3f0.4 on # APC end device pnp 3f0.5 on # PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end device pnp 3f0.6 on # PS/2 mouse irq 0x70 = 12 end device pnp 3f0.7 on # GPIO end end end device pci 7.1 on end # IDE device pci 7.2 on end # USB device pci 7.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" # Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" register "ide1_drive1_udma33_enable" = "0" end end end