## we don't use CONFIG_USE_DCACHE_RAM by default
default CONFIG_USE_DCACHE_RAM=0
##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
default CONFIG_ROM_SIZE = 256 * 1024 
default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_IMAGE_SIZE
default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE

##
## Compute where this copy of coreboot will start in the boot rom
##
default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)

##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
##
default CONFIG_XIP_ROM_SIZE=32*1024
default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
#object reset.o


## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. 
## That way, later, we can simply yank them if we wish. 
## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. 
## we do not use failover yet in this case. This is a work in progress. 
if CONFIG_USE_DCACHE_RAM
	##
	##
	mainboardinit arch/i386/init/entry.S
	mainboardinit arch/i386/init/car.S
	ldscript  /arch/i386/init/ldscript.ld

	## The main code for the rom section is called rom.c
	initobject rom.o
else
	##
	## Romcc output
	##
	makerule ./failover.E
		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
	end
	
	makerule ./failover.inc
		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
	end
	
	makerule ./auto.E 
		depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
		action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
	end
	makerule ./auto.inc 
		depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
		action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
	end
	
	##
	## Build our 16 bit and 32 bit coreboot entry code
	##
	mainboardinit cpu/x86/16bit/entry16.inc
	mainboardinit cpu/x86/32bit/entry32.inc
	ldscript /cpu/x86/16bit/entry16.lds
	ldscript /cpu/x86/32bit/entry32.lds

	##
	## Build our reset vector (This is where coreboot is entered)
	##
	mainboardinit cpu/x86/16bit/reset16.inc 
	ldscript /cpu/x86/16bit/reset16.lds 
	
	### Should this be in the northbridge code?
	mainboardinit arch/i386/lib/cpu_reset.inc

	##
	## Setup RAM
	##
	mainboardinit cpu/x86/fpu_enable.inc
	mainboardinit ./auto.inc
	
	## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future. 
	##
	## Include an id string (For safe flashing)
	##
	mainboardinit arch/i386/lib/id.inc
	ldscript /arch/i386/lib/id.lds
	
##
## end of CONFIG_USE_DCACHE_RAM bits. 
##
end

##
## Include the secondary Configuration files 
##
dir /pc80
config chip.h

chip cpu/emulation/qemu-x86
	device pci_domain 0 on 
		device pci 0.0 on end

		chip southbridge/intel/i82371eb # southbridge
			device pci 01.0 on end
			device pci 01.1 on end
			register "ide0_enable" = "1"
			register "ide1_enable" = "1"
		end

#		register "com1" = "{1}"
#		register "com1" = "{1, 0, 0x3f8, 4}"
	end
end