##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

chip northbridge/amd/amdk8/root_complex		# Root complex
  device lapic_cluster 0 on			# (L)APIC cluster
    chip cpu/amd/socket_AM2			# CPU socket
      device lapic 0 on end			# Local APIC of the CPU
    end
  end
  device pci_domain 0 on			# PCI domain
    chip northbridge/amd/amdk8			# Northbridge / RAM controller
      device pci 18.0 on			# Link 0 == LDT 0
        chip southbridge/nvidia/mcp55		# Southbridge
          device pci 0.0 on end			# HT
          device pci 1.0 on			# LPC
            chip superio/ite/it8716f		# Super I/O
              device pnp 2e.0 on		# Floppy
                io 0x60 = 0x3f0
                irq 0x70 = 6
                drq 0x74 = 2
              end
              device pnp 2e.1 on		# Com1
                io 0x60 = 0x3f8
                irq 0x70 = 4
              end
              device pnp 2e.2 off		# Com2 (N/A)
              end
              device pnp 2e.3 on		# Parallel port
                io 0x60 = 0x378
                io 0x62 = 0x000
                irq 0x70 = 7
                drq 0x74 = 4
              end
              device pnp 2e.4 on		# Environment controller
                io 0x60 = 0x290
                io 0x62 = 0x000
                irq 0x70 = 0
              end
              device pnp 2e.5 on		# PS/2 keyboard
                io 0x60 = 0x60
                io 0x62 = 0x64
                irq 0x70 = 1			# PS/2 keyboard IRQ
              end
              device pnp 2e.6 on		# PS/2 mouse
                irq 0x70 = 12			# PS/2 mouse IRQ
              end
              device pnp 2e.7 off		# GPIO
                io 0x60 = 0x0000		# SMI# Normal Run Access
                io 0x62 = 0x800			# Simple I/O
                io 0x64 = 0x0000		# Serial Flash I/F
              end
              device pnp 2e.8 off		# MIDI (N/A)
              end
              device pnp 2e.9 off		# Game port (N/A)
              end
              device pnp 2e.a off		# Consumer IR (N/A)
              end
            end
          end
          device pci 1.1 on			# SM 0
            chip drivers/generic/generic	# DIMM 0-0-0
              device i2c 50 on end
            end
            chip drivers/generic/generic	# DIMM 0-0-1
              device i2c 51 on end
            end
            chip drivers/generic/generic	# DIMM 0-1-0
              device i2c 52 on end
            end
            chip drivers/generic/generic	# DIMM 0-1-1
              device i2c 53 on end
            end
          end
          device pci 2.0 on end			# USB 1.1
          device pci 2.1 on end			# USB 2
          device pci 4.0 on end			# IDE
          device pci 5.0 on end			# SATA 0
          device pci 5.1 on end			# SATA 1
          device pci 5.2 on end			# SATA 2
          device pci 6.0 on end			# PCI
          device pci 6.1 on end			# Azalia (HD Audio)
          device pci 8.0 on end			# NIC
          device pci 9.0 off end		# NIC (N/A)
          device pci a.0 on end			# PCI E 5 (PCIEX4)
          device pci b.0 off end		# PCI E 4
          device pci c.0 on end			# PCI E 3 (PCIEX1_2)
          device pci d.0 on end			# PCI E 2 (PCIEX1_1)
          device pci e.0 off end		# PCI E 1
          device pci f.0 off end		# PCI E 0
          register "ide0_enable" = "1"		# Primary IDE
          register "ide1_enable" = "0"		# Secondary IDE (N/A)
          register "sata0_enable" = "1"
          register "sata1_enable" = "1"
        end
      end
      device pci 18.0 on end			# Link 1
      device pci 18.0 on end
      device pci 18.1 on end
      device pci 18.2 on end
      device pci 18.3 on end
    end
  end
end