## ## This file is part of the LinuxBIOS project. ## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu for AMD. ## ## Copyright (C) 2007 Rudolf Marek ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) default ROM_SECTION_OFFSET = 0 end ## ## Compute the start location and size size of ## The linuxBIOS bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 ## ## Compute where this copy of linuxBIOS will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up linuxBIOS, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) arch i386 end ## ## Build the objects we have code for in this directory. ## driver mainboard.o if HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c depends "$(MAINBOARD)/dsdt.asl" action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o end if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end end end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds mainboardinit southbridge/via/k8t890/romstrap.inc ldscript /southbridge/via/k8t890/romstrap.lds end mainboardinit cpu/x86/32bit/entry32.inc if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end end ## ## Build our reset vector (This is where linuxBIOS is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc end ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds end end ## ## Setup RAM ## if USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end end ## ## Include the secondary Configuration files ## if CONFIG_CHIP_NAME config chip.h end chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_939 device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 #mc0 device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/via/vt8237r #both IDE channels register "ide0_enable" = "1" register "ide1_enable" = "1" #both cables are 80pin register "ide0_80pin_cable" = "1" register "ide1_80pin_cable" = "1" #enables the functions of SB register "fn_ctrl_lo" = "0" register "fn_ctrl_hi" = "0xad" device pci 0.0 on end # HT device pci f.1 on end # IDE device pci 11.0 on # LPC chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end end chip superio/winbond/w83627ehg device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.5 off #keyb OFF end device pnp 2e.6 off # SERIAL_FLASH io 0x60 = 0x100 end device pnp 2e.7 off # GAME_MIDI_GIPO1 # io 0x60 = 0x220 # io 0x62 = 0x300 # irq 0x70 = a end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 0x30 0x9 #GPIO 5 and 2 active #0xe0 = de #0xe1 = 01 #0xe2 = 00 #0xe3 = 03 #0xe4 = a4 #0xe5 = 00 device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 0 end end #end SIO end #end 11 device pci 12.0 off end # VIA LAN is disabled, Asus used other chip end chip southbridge/via/k8t890 end end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end #mc0 end # pci_domain end # root_complex