/* * SGen is licensed under the terms of the MIT X11 license * * Copyright 2001-2003 Ximian, Inc * Copyright 2003-2010 Novell, Inc. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __MONO_SGENARCHDEP_H__ #define __MONO_SGENARCHDEP_H__ #include #ifdef __i386__ #include #define REDZONE_SIZE 0 #define ARCH_NUM_REGS 8 #ifdef MONO_ARCH_HAS_MONO_CONTEXT #define USE_MONO_CTX #else #define ARCH_STORE_REGS(ptr) \ __asm__ __volatile__( \ "mov %%edi,0(%0)\n" \ "mov %%esi,4(%0)\n" \ "mov %%ebx,8(%0)\n" \ "mov %%edx,12(%0)\n" \ "mov %%ecx,16(%0)\n" \ "mov %%eax,20(%0)\n" \ "mov %%ebp,24(%0)\n" \ "mov %%esp,28(%0)\n" \ : \ : "r" (ptr) \ ) #endif /*FIXME, move this to mono-sigcontext as this is generaly useful.*/ #define ARCH_SIGCTX_SP(ctx) (UCONTEXT_REG_ESP ((ctx))) #define ARCH_SIGCTX_IP(ctx) (UCONTEXT_REG_EIP ((ctx))) #elif defined(__x86_64__) #include #define REDZONE_SIZE 128 #define ARCH_NUM_REGS 16 #define USE_MONO_CTX /*FIXME, move this to mono-sigcontext as this is generaly useful.*/ #define ARCH_SIGCTX_SP(ctx) (UCONTEXT_REG_RSP (ctx)) #define ARCH_SIGCTX_IP(ctx) (UCONTEXT_REG_RIP (ctx)) #elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__) #define REDZONE_SIZE 224 #define ARCH_NUM_REGS 32 #ifdef __APPLE__ #define ARCH_STORE_REGS(ptr) \ __asm__ __volatile__( \ "stmw r0, 0(%0)\n" \ : \ : "b" (ptr) \ ) #else #define ARCH_STORE_REGS(ptr) \ __asm__ __volatile__( \ "stmw 0, 0(%0)\n" \ : \ : "b" (ptr) \ ) #endif #define ARCH_SIGCTX_SP(ctx) (UCONTEXT_REG_Rn((ctx), 1)) #define ARCH_SIGCTX_IP(ctx) (UCONTEXT_REG_NIP((ctx))) #define ARCH_COPY_SIGCTX_REGS(a,ctx) do { \ int __i; \ for (__i = 0; __i < 32; ++__i) \ ((a)[__i]) = UCONTEXT_REG_Rn((ctx), __i); \ } while (0) #elif defined(__arm__) #define REDZONE_SIZE 0 /* We dont store ip, sp */ #define ARCH_NUM_REGS 14 #define ARCH_STORE_REGS(ptr) \ __asm__ __volatile__( \ "push {lr}\n" \ "mov lr, %0\n" \ "stmia lr!, {r0-r12}\n" \ "pop {lr}\n" \ : \ : "r" (ptr) \ ) #define ARCH_SIGCTX_SP(ctx) (UCONTEXT_REG_SP((ctx))) #define ARCH_SIGCTX_IP(ctx) (UCONTEXT_REG_PC((ctx))) #define ARCH_COPY_SIGCTX_REGS(a,ctx) do { \ ((a)[0]) = (gpointer) (UCONTEXT_REG_R0((ctx))); \ ((a)[1]) = (gpointer) (UCONTEXT_REG_R1((ctx))); \ ((a)[2]) = (gpointer) (UCONTEXT_REG_R2((ctx))); \ ((a)[3]) = (gpointer) (UCONTEXT_REG_R3((ctx))); \ ((a)[4]) = (gpointer) (UCONTEXT_REG_R4((ctx))); \ ((a)[5]) = (gpointer) (UCONTEXT_REG_R5((ctx))); \ ((a)[6]) = (gpointer) (UCONTEXT_REG_R6((ctx))); \ ((a)[7]) = (gpointer) (UCONTEXT_REG_R7((ctx))); \ ((a)[8]) = (gpointer) (UCONTEXT_REG_R8((ctx))); \ ((a)[9]) = (gpointer) (UCONTEXT_REG_R9((ctx))); \ ((a)[10]) = (gpointer) (UCONTEXT_REG_R10((ctx))); \ ((a)[11]) = (gpointer) (UCONTEXT_REG_R11((ctx))); \ ((a)[12]) = (gpointer) (UCONTEXT_REG_R12((ctx))); \ ((a)[13]) = (gpointer) (UCONTEXT_REG_LR((ctx))); \ } while (0) #elif defined(__mips__) #define REDZONE_SIZE 0 #define ARCH_NUM_REGS 32 #define ARCH_STORE_REGS(ptr) \ __asm__ __volatile__( \ "sw $0,0(%0)\n\t" \ "sw $1,4(%0)\n\t" \ "sw $2,8(%0)\n\t" \ "sw $3,12(%0)\n\t" \ "sw $4,16(%0)\n\t" \ "sw $5,20(%0)\n\t" \ "sw $6,24(%0)\n\t" \ "sw $7,28(%0)\n\t" \ "sw $8,32(%0)\n\t" \ "sw $9,36(%0)\n\t" \ "sw $10,40(%0)\n\t" \ "sw $11,44(%0)\n\t" \ "sw $12,48(%0)\n\t" \ "sw $13,52(%0)\n\t" \ "sw $14,56(%0)\n\t" \ "sw $15,60(%0)\n\t" \ "sw $16,64(%0)\n\t" \ "sw $17,68(%0)\n\t" \ "sw $18,72(%0)\n\t" \ "sw $19,76(%0)\n\t" \ "sw $20,80(%0)\n\t" \ "sw $21,84(%0)\n\t" \ "sw $22,88(%0)\n\t" \ "sw $23,92(%0)\n\t" \ "sw $24,96(%0)\n\t" \ "sw $25,100(%0)\n\t" \ "sw $26,104(%0)\n\t" \ "sw $27,108(%0)\n\t" \ "sw $28,112(%0)\n\t" \ "sw $29,116(%0)\n\t" \ "sw $30,120(%0)\n\t" \ "sw $31,124(%0)\n\t" \ : \ : "r" (ptr) \ : "memory" \ ) #define ARCH_SIGCTX_SP(ctx) (UCONTEXT_GREGS((ctx))[29]) #define ARCH_SIGCTX_IP(ctx) (UCONTEXT_REG_PC((ctx))) #define ARCH_COPY_SIGCTX_REGS(a,ctx) do { \ int __regnum; \ for (__regnum = 0; __regnum < 32; ++__regnum) \ ((a)[__regnum]) = (gpointer) (UCONTEXT_GREGS((ctx))[__regnum]); \ } while (0) #elif defined(__s390x__) #define REDZONE_SIZE 0 #include #define USE_MONO_CTX #define ARCH_NUM_REGS 16 #define ARCH_SIGCTX_SP(ctx) ((UCONTEXT_GREGS((ctx))) [15]) #define ARCH_SIGCTX_IP(ctx) ((ucontext_t *) (ctx))->uc_mcontext.psw.addr #elif defined(__sparc__) #define REDZONE_SIZE 0 /* Don't bother with %g0 (%r0), it's always hard-coded to zero */ #define ARCH_NUM_REGS 15 #ifdef __sparcv9 #define ARCH_STORE_REGS(ptr) \ __asm__ __volatile__( \ "st %%g1,[%0]\n\t" \ "st %%g2,[%0+0x08]\n\t" \ "st %%g3,[%0+0x10]\n\t" \ "st %%g4,[%0+0x18]\n\t" \ "st %%g5,[%0+0x20]\n\t" \ "st %%g6,[%0+0x28]\n\t" \ "st %%g7,[%0+0x30]\n\t" \ "st %%o0,[%0+0x38]\n\t" \ "st %%o1,[%0+0x40]\n\t" \ "st %%o2,[%0+0x48]\n\t" \ "st %%o3,[%0+0x50]\n\t" \ "st %%o4,[%0+0x58]\n\t" \ "st %%o5,[%0+0x60]\n\t" \ "st %%o6,[%0+0x68]\n\t" \ "st %%o7,[%0+0x70]\n\t" \ : \ : "r" (ptr) \ : "memory" \ ) #else #define ARCH_STORE_REGS(ptr) \ __asm__ __volatile__( \ "st %%g1,[%0]\n\t" \ "st %%g2,[%0+0x04]\n\t" \ "st %%g3,[%0+0x08]\n\t" \ "st %%g4,[%0+0x0c]\n\t" \ "st %%g5,[%0+0x10]\n\t" \ "st %%g6,[%0+0x14]\n\t" \ "st %%g7,[%0+0x18]\n\t" \ "st %%o0,[%0+0x1c]\n\t" \ "st %%o1,[%0+0x20]\n\t" \ "st %%o2,[%0+0x24]\n\t" \ "st %%o3,[%0+0x28]\n\t" \ "st %%o4,[%0+0x2c]\n\t" \ "st %%o5,[%0+0x30]\n\t" \ "st %%o6,[%0+0x34]\n\t" \ "st %%o7,[%0+0x38]\n\t" \ : \ : "r" (ptr) \ : "memory" \ ) #endif #define ARCH_SIGCTX_SP(ctx) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_SP]) #define ARCH_SIGCTX_IP(ctx) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_PC]) #define ARCH_COPY_SIGCTX_REGS(a,ctx) do { \ (a)[0] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_G1]); \ (a)[1] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_G2]); \ (a)[2] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_G3]); \ (a)[3] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_G4]); \ (a)[4] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_G5]); \ (a)[5] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_G6]); \ (a)[6] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_G7]); \ (a)[7] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_O0]); \ (a)[8] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_O1]); \ (a)[9] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_O2]); \ (a)[10] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_O3]); \ (a)[11] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_O4]); \ (a)[12] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_O5]); \ (a)[13] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_O6]); \ (a)[14] = (gpointer) (((ucontext_t *)(ctx))->uc_mcontext.gregs [REG_O7]); \ } while (0) #endif #endif /* __MONO_SGENARCHDEP_H__ */