Classic Timing Analyzer report for dt Thu Dec 16 16:55:05 2010 Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Classic Timing Analyzer Deprecation 3. Timing Analyzer Summary 4. Timing Analyzer Settings 5. Clock Settings Summary 6. Parallel Compilation 7. Clock Setup: 'sys_clk' 8. tco 9. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. --------------------------------------- ; Classic Timing Analyzer Deprecation ; --------------------------------------- Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Summary ; +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+ ; Worst-case tco ; N/A ; None ; 8.846 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ; ; Clock Setup: 'sys_clk' ; N/A ; None ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; +------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Settings ; +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ ; Option ; Setting ; From ; To ; Entity Name ; +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ ; Device Name ; EP1C12Q240C8 ; ; ; ; ; Timing Models ; Final ; ; ; ; ; Default hold multicycle ; Same as Multicycle ; ; ; ; ; Cut paths between unrelated clock domains ; On ; ; ; ; ; Cut off read during write signal paths ; On ; ; ; ; ; Cut off feedback from I/O pins ; On ; ; ; ; ; Report Combined Fast/Slow Timing ; Off ; ; ; ; ; Ignore Clock Settings ; Off ; ; ; ; ; Analyze latches as synchronous elements ; On ; ; ; ; ; Enable Recovery/Removal analysis ; Off ; ; ; ; ; Enable Clock Latency ; Off ; ; ; ; ; Use TimeQuest Timing Analyzer ; Off ; ; ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; ; ; Number of source nodes to report per destination node ; 10 ; ; ; ; ; Number of destination nodes to report ; 10 ; ; ; ; ; Number of paths to report ; 200 ; ; ; ; ; Report Minimum Timing Checks ; Off ; ; ; ; ; Use Fast Timing Models ; Off ; ; ; ; ; Report IO Paths Separately ; Off ; ; ; ; ; Perform Multicorner Analysis ; Off ; ; ; ; ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; ; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ; ; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ; ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Settings Summary ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ ; sys_clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 2 ; ; Maximum allowed ; 1 ; +----------------------------+--------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Setup: 'sys_clk' ; +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ; ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ; ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ; ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ; ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ; ; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ; ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ; ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ; ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ; ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ; ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ; ; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ; ; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ; ; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ; ; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ; ; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ; ; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ; ; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ; ; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ; ; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ; ; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ; ; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ; ; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ; ; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ; ; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ; ; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ; ; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ; ; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ; ; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ; ; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ; ; N/A ; 59.51 MHz ( period = 16.805 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.544 ns ; ; N/A ; 59.51 MHz ( period = 16.805 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.544 ns ; ; N/A ; 59.73 MHz ( period = 16.743 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.473 ns ; ; N/A ; 59.73 MHz ( period = 16.743 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.473 ns ; ; N/A ; 60.26 MHz ( period = 16.594 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.324 ns ; ; N/A ; 60.26 MHz ( period = 16.594 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.324 ns ; ; N/A ; 60.70 MHz ( period = 16.475 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.205 ns ; ; N/A ; 60.70 MHz ( period = 16.475 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.205 ns ; ; N/A ; 61.33 MHz ( period = 16.306 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.036 ns ; ; N/A ; 61.33 MHz ( period = 16.306 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.036 ns ; ; N/A ; 62.02 MHz ( period = 16.125 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.797 ns ; ; N/A ; 62.17 MHz ( period = 16.085 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.815 ns ; ; N/A ; 62.17 MHz ( period = 16.085 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.815 ns ; ; N/A ; 62.25 MHz ( period = 16.063 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.726 ns ; ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ; ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ; ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ; ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ; ; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ; ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ; ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ; ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ; ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ; ; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ; ; N/A ; 62.84 MHz ( period = 15.914 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.577 ns ; ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ; ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ; ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ; ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ; ; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ; ; N/A ; 63.24 MHz ( period = 15.812 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.542 ns ; ; N/A ; 63.24 MHz ( period = 15.812 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.542 ns ; ; N/A ; 63.31 MHz ( period = 15.795 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.458 ns ; ; N/A ; 63.53 MHz ( period = 15.741 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.480 ns ; ; N/A ; 63.53 MHz ( period = 15.741 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.480 ns ; ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ; ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ; ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ; ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ; ; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ; ; N/A ; 64.00 MHz ( period = 15.626 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.289 ns ; ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ; ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ; ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ; ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ; ; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ; ; N/A ; 64.86 MHz ( period = 15.417 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.156 ns ; ; N/A ; 64.86 MHz ( period = 15.417 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.156 ns ; ; N/A ; 64.91 MHz ( period = 15.405 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.068 ns ; ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ; ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ; ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ; ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ; ; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ; ; N/A ; 66.09 MHz ( period = 15.132 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.795 ns ; ; N/A ; 66.12 MHz ( period = 15.123 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.862 ns ; ; N/A ; 66.40 MHz ( period = 15.061 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.733 ns ; ; N/A ; 66.40 MHz ( period = 15.061 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.791 ns ; ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ; ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ; ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ; ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ; ; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ; ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ; ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ; ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ; ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ; ; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ; ; N/A ; 67.06 MHz ( period = 14.912 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.642 ns ; ; N/A ; 67.32 MHz ( period = 14.854 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.593 ns ; ; N/A ; 67.32 MHz ( period = 14.854 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.593 ns ; ; N/A ; 67.60 MHz ( period = 14.793 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.523 ns ; ; N/A ; 67.86 MHz ( period = 14.737 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.409 ns ; ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ; ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ; ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ; ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ; ; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ; ; N/A ; 68.38 MHz ( period = 14.624 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.354 ns ; ; N/A ; 68.41 MHz ( period = 14.618 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.424 ns ; ; N/A ; 68.41 MHz ( period = 14.618 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.424 ns ; ; N/A ; 68.73 MHz ( period = 14.549 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.288 ns ; ; N/A ; 68.73 MHz ( period = 14.549 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.288 ns ; ; N/A ; 68.77 MHz ( period = 14.541 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.280 ns ; ; N/A ; 68.77 MHz ( period = 14.541 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.280 ns ; ; N/A ; 69.24 MHz ( period = 14.443 ns ) ; decode_stage:decode_st|rtw_rec.immediate[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.182 ns ; ; N/A ; 69.24 MHz ( period = 14.443 ns ) ; decode_stage:decode_st|rtw_rec.immediate[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.182 ns ; ; N/A ; 69.43 MHz ( period = 14.403 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.133 ns ; ; N/A ; 69.48 MHz ( period = 14.393 ns ) ; execute_stage:exec_st|reg.result[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.132 ns ; ; N/A ; 69.48 MHz ( period = 14.393 ns ) ; execute_stage:exec_st|reg.result[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.132 ns ; ; N/A ; 69.59 MHz ( period = 14.369 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.108 ns ; ; N/A ; 69.59 MHz ( period = 14.369 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.108 ns ; ; N/A ; 70.14 MHz ( period = 14.258 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.997 ns ; ; N/A ; 70.14 MHz ( period = 14.258 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.997 ns ; ; N/A ; 70.48 MHz ( period = 14.189 ns ) ; execute_stage:exec_st|reg.result[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.928 ns ; ; N/A ; 70.48 MHz ( period = 14.189 ns ) ; execute_stage:exec_st|reg.result[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.928 ns ; ; N/A ; 70.55 MHz ( period = 14.175 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.905 ns ; ; N/A ; 70.55 MHz ( period = 14.175 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.905 ns ; ; N/A ; 70.55 MHz ( period = 14.174 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.846 ns ; ; N/A ; 70.64 MHz ( period = 14.156 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.828 ns ; ; N/A ; 70.77 MHz ( period = 14.130 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 13.860 ns ; ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ; ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ; ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ; ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ; ; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ; ; N/A ; 70.95 MHz ( period = 14.094 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.757 ns ; ; N/A ; 71.06 MHz ( period = 14.072 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[5] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.811 ns ; ; N/A ; 71.06 MHz ( period = 14.072 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[5] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.811 ns ; ; N/A ; 71.13 MHz ( period = 14.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 13.798 ns ; ; N/A ; 71.71 MHz ( period = 13.945 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.608 ns ; ; N/A ; 71.73 MHz ( period = 13.942 ns ) ; decode_stage:decode_st|rtw_rec.immediate[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.681 ns ; ; N/A ; 71.73 MHz ( period = 13.942 ns ) ; decode_stage:decode_st|rtw_rec.immediate[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.681 ns ; ; N/A ; 71.75 MHz ( period = 13.938 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.677 ns ; ; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ; ; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ; ; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ; ; N/A ; 72.07 MHz ( period = 13.875 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[10] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.614 ns ; ; N/A ; 72.07 MHz ( period = 13.875 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[10] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.614 ns ; ; N/A ; 72.10 MHz ( period = 13.869 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.541 ns ; ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ; ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ; ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ; ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ; ; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ; ; N/A ; 72.14 MHz ( period = 13.861 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.533 ns ; ; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ; ; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ; ; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ; ; N/A ; 72.33 MHz ( period = 13.826 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.489 ns ; ; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ; ; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ; ; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ; ; N/A ; 72.47 MHz ( period = 13.799 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[13] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.529 ns ; ; N/A ; 72.47 MHz ( period = 13.799 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[13] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.529 ns ; ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 13.093 ns ; ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ; ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ; ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ; ; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------+ ; tco ; +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+ ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+ ; N/A ; None ; 8.846 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; +-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+ +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus II Classic Timing Analyzer Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition Info: Processing started: Thu Dec 16 16:55:05 2010 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents. Warning: Found pins functioning as undefined clocks and/or memory enables Info: Assuming node "sys_clk" is an undefined clock Info: Clock "sys_clk" has Internal fmax of 49.7 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]" (period= 20.119 ns) Info: + Longest memory to register delay is 19.416 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y16; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0' Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a9' Info: 3: + IC(1.893 ns) + CELL(0.114 ns) = 6.324 ns; Loc. = LC_X27_Y12_N5; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[9]~23' Info: 4: + IC(0.416 ns) + CELL(0.114 ns) = 6.854 ns; Loc. = LC_X27_Y12_N2; Fanout = 6; COMB Node = 'execute_stage:exec_st|left_operand[9]~24' Info: 5: + IC(1.990 ns) + CELL(0.564 ns) = 9.408 ns; Loc. = LC_X28_Y13_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~52' Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 9.586 ns; Loc. = LC_X28_Y13_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~57' Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 9.794 ns; Loc. = LC_X28_Y13_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~77' Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 10.473 ns; Loc. = LC_X28_Y12_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~90' Info: 9: + IC(1.498 ns) + CELL(0.114 ns) = 12.085 ns; Loc. = LC_X32_Y12_N1; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~14' Info: 10: + IC(0.428 ns) + CELL(0.590 ns) = 13.103 ns; Loc. = LC_X32_Y12_N2; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~17' Info: 11: + IC(1.142 ns) + CELL(0.590 ns) = 14.835 ns; Loc. = LC_X29_Y12_N8; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~23' Info: 12: + IC(1.556 ns) + CELL(0.114 ns) = 16.505 ns; Loc. = LC_X28_Y11_N8; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1' Info: 13: + IC(2.044 ns) + CELL(0.867 ns) = 19.416 ns; Loc. = LC_X36_Y14_N5; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]' Info: Total cell delay = 8.449 ns ( 43.52 % ) Info: Total interconnect delay = 10.967 ns ( 56.48 % ) Info: - Smallest clock skew is -0.016 ns Info: + Shortest clock path from clock "sys_clk" to destination register is 3.178 ns Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk' Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X36_Y14_N5; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]' Info: Total cell delay = 2.180 ns ( 68.60 % ) Info: Total interconnect delay = 0.998 ns ( 31.40 % ) Info: - Longest clock path from clock "sys_clk" to source memory is 3.194 ns Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk' Info: 2: + IC(1.007 ns) + CELL(0.718 ns) = 3.194 ns; Loc. = M4K_X33_Y16; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0' Info: Total cell delay = 2.187 ns ( 68.47 % ) Info: Total interconnect delay = 1.007 ns ( 31.53 % ) Info: + Micro clock to output delay of source is 0.650 ns Info: + Micro setup delay of destination is 0.037 ns Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 8.846 ns Info: + Longest clock path from clock "sys_clk" to source register is 3.178 ns Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk' Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X36_Y14_N2; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int' Info: Total cell delay = 2.180 ns ( 68.60 % ) Info: Total interconnect delay = 0.998 ns ( 31.40 % ) Info: + Micro clock to output delay of source is 0.224 ns Info: + Longest register to pin delay is 5.444 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y14_N2; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int' Info: 2: + IC(3.320 ns) + CELL(2.124 ns) = 5.444 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx' Info: Total cell delay = 2.124 ns ( 39.02 % ) Info: Total interconnect delay = 3.320 ns ( 60.98 % ) Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings Info: Peak virtual memory: 187 megabytes Info: Processing ended: Thu Dec 16 16:55:06 2010 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01