Design Assistant report for dt Mon Dec 20 17:39:01 2010 Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Design Assistant Summary 3. Design Assistant Settings 4. High Violations 5. Medium Violations 6. Information only Violations 7. Design Assistant Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------+ ; Design Assistant Summary ; +-----------------------------------+-------------------------------------+ ; Design Assistant Status ; Analyzed - Mon Dec 20 17:39:01 2010 ; ; Revision Name ; dt ; ; Top-level Entity Name ; core_top ; ; Family ; Cyclone ; ; Total Critical Violations ; 0 ; ; Total High Violations ; 12 ; ; - Rule S102 ; 12 ; ; Total Medium Violations ; 1 ; ; - Rule R102 ; 1 ; ; Total Information only Violations ; 99 ; ; - Rule T101 ; 49 ; ; - Rule T102 ; 50 ; +-----------------------------------+-------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Design Assistant Settings ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ ; Option ; Setting ; To ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ ; Design Assistant mode ; Post-Fitting ; ; ; Threshold value for clock net not mapped to clock spines rule ; 25 ; ; ; Minimum number of clock port feed by gated clocks ; 30 ; ; ; Minimum number of node fan-out ; 30 ; ; ; Maximum number of nodes to report ; 50 ; ; ; Rule C101: Gated clock should be implemented according to the Altera standard scheme ; On ; ; ; Rule C102: Logic cell should not be used to generate an inverted clock signal ; On ; ; ; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; On ; ; ; Rule C104: Clock signal source should drive only clock input ports ; On ; ; ; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On ; ; ; Rule C106: Clock signal source should not drive registers triggered by different clock edges ; On ; ; ; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ; ; Rule R102: External reset signals should be synchronized using two cascaded registers ; On ; ; ; Rule R103: External reset signal should be correctly synchronized ; On ; ; ; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized ; On ; ; ; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized ; On ; ; ; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ; ; Rule T102: Top nodes with the highest number of fan-outs ; On ; ; ; Rule A101: Design should not contain combinational loops ; On ; ; ; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ; ; Rule A103: Design should not contain delay chains ; On ; ; ; Rule A104: Design should not contain ripple clock structures ; On ; ; ; Rule A105: Pulses should not be implemented asynchronously ; On ; ; ; Rule A106: Multiple pulses should not be generated in design ; On ; ; ; Rule A107: Design should not contain SR latches ; On ; ; ; Rule A108: Design should not contain latches ; On ; ; ; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ; ; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source ; On ; ; ; Rule S104: Clock port and any other port of a register should not be driven by the same signal source ; On ; ; ; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ; ; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ; ; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ; ; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains ; Off ; ; ; Rule M102: No reset signal defined to initialize the state machine ; Off ; ; ; Rule M103: State machine should not contain an unreachable state ; Off ; ; ; Rule M104: State machine should not contain a deadlock state ; Off ; ; ; Rule M105: State machine should not contain a dead transition ; Off ; ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; High Violations ; +-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+ ; Rule name ; Name ; +-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+ ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; execute_stage:exec_st|reg.alu_jump ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[0] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[1] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[2] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[3] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[4] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[5] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[6] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[7] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[8] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[9] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[10] ; ; Synchronous and reset port source node(s) list ; sys_res ; +-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Medium Violations ; +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+ ; Rule name ; Name ; +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+ ; Rule R102: External reset signals should be synchronized using two cascaded registers ; sys_res ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ; ; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ; +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Information only Violations ; +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+ ; Rule name ; Name ; Fan-Out ; +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+ ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 96 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 63 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 53 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[0]~25 ; 100 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; sys_clk ; 569 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; sys_res ; 549 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.imm_set ; 65 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~13 ; 42 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND ; 208 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16 ; 33 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 60 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 109 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 42 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 56 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 50 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 34 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[3]~22 ; 71 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 78 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_out~2 ; 80 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072 ; 71 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 75 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1 ; 33 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31]~0 ; 31 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[3] ; 39 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[2] ; 64 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31]~0 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 40 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2 ; 31 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 64 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector0~0 ; 35 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ; ; Rule T102: Top nodes with the highest number of fan-outs ; sys_clk ; 569 ; ; Rule T102: Top nodes with the highest number of fan-outs ; sys_res ; 549 ; ; Rule T102: Top nodes with the highest number of fan-outs ; ~GND ; 208 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 109 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[0]~25 ; 100 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 96 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_out~2 ; 80 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 78 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 75 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[3]~22 ; 71 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072 ; 71 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.imm_set ; 65 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 64 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[2] ; 64 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 63 ; ; Rule T102: Top nodes with the highest number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 60 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 56 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 53 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 50 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[1]~13 ; 42 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 42 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 40 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[3] ; 39 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector0~0 ; 35 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 34 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16 ; 33 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ; ; Rule T102: Top nodes with the highest number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1 ; 33 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31]~0 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31]~0 ; 31 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2 ; 31 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|pwr_en~4 ; 30 ; +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+ +---------------------------+ ; Design Assistant Messages ; +---------------------------+ Info: ******************************************************************* Info: Running Quartus II Design Assistant Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition Info: Processing started: Mon Dec 20 17:38:59 2010 Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off dt -c dt Critical Warning: Synopsys Design Constraints File file not found: 'dt.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info: No user constrained base clocks found in the design Critical Warning: (High) Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source. Found 12 node(s) related to this rule. Critical Warning: Node "execute_stage:exec_st|reg.alu_jump" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[0]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[1]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[2]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[3]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[4]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[5]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[6]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[7]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[8]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[9]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[10]" Warning: (Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule. Warning: Node "sys_res" Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 49 node(s) with highest fan-out. Info: Node "execute_stage:exec_st|right_operand[1]~19" Info: Node "writeback_stage:writeback_st|wb_reg.dmem_en" Info: Node "execute_stage:exec_st|left_operand[5]~3" Info: Node "execute_stage:exec_st|right_operand[0]~25" Info: Node "sys_clk" Info: Node "sys_res" Info: Node "decode_stage:decode_st|rtw_rec.imm_set" Info: Node "execute_stage:exec_st|right_operand[1]~13" Info: Node "decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0" Info: Node "~GND" Info: Node "decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16" Info: Node "writeback_stage:writeback_st|data_addr[2]~0" Info: Node "writeback_stage:writeback_st|data_addr[3]~1" Info: Node "writeback_stage:writeback_st|data_addr[4]~2" Info: Node "writeback_stage:writeback_st|data_addr[5]~3" Info: Node "writeback_stage:writeback_st|data_addr[7]~5" Info: Node "writeback_stage:writeback_st|data_addr[8]~6" Info: Node "writeback_stage:writeback_st|data_addr[9]~7" Info: Node "writeback_stage:writeback_st|data_addr[10]~8" Info: Node "writeback_stage:writeback_st|data_addr[11]~9" Info: Node "writeback_stage:writeback_st|data_addr[12]~10" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP" Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[1]" Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0" Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.STACK_OP" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP" Info: Node "writeback_stage:writeback_st|wb_reg.address[13]" Info: Node "execute_stage:exec_st|right_operand[3]~22" Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]" Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated. Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out. Info: Node "sys_clk" Info: Node "sys_res" Info: Node "~GND" Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[1]" Info: Node "execute_stage:exec_st|right_operand[0]~25" Info: Node "execute_stage:exec_st|right_operand[1]~19" Info: Node "writeback_stage:writeback_st|data_out~2" Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]" Info: Node "execute_stage:exec_st|right_operand[2]~16" Info: Node "execute_stage:exec_st|right_operand[3]~22" Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072" Info: Node "decode_stage:decode_st|rtw_rec.imm_set" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.OR_OP" Info: Node "writeback_stage:writeback_st|wb_reg.address[2]" Info: Node "writeback_stage:writeback_st|wb_reg.dmem_en" Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.STACK_OP" Info: Node "execute_stage:exec_st|left_operand[5]~3" Info: Node "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP" Info: Node "execute_stage:exec_st|right_operand[1]~13" Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP" Info: Node "writeback_stage:writeback_st|wb_reg.address[3]" Info: Node "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP" Info: Node "execute_stage:exec_st|alu:alu_inst|Selector0~0" Info: Node "writeback_stage:writeback_st|wb_reg.address[13]" Info: Node "decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP" Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated. Info: Design Assistant information: finished post-fitting analysis of current design -- generated 99 information messages and 13 warning messages Info: Quartus II Design Assistant was successful. 0 errors, 16 warnings Info: Peak virtual memory: 195 megabytes Info: Processing ended: Mon Dec 20 17:39:01 2010 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02