--   `Deep Thought', a softcore CPU implemented on a FPGA
--
--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

package mem_pkg is

	component r_w_ram is
	generic	(
				ADDR_WIDTH : integer range 1 to integer'high;
				DATA_WIDTH : integer range 1 to integer'high
			);
	port(
		--System inputs
			clk : in std_logic;
		--Input
			wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
			
			wr_en : in std_logic;
			data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
			
		--Output
			data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
		);
	end component r_w_ram;

	component r_w_ram_be is
	generic	(
				ADDR_WIDTH : integer range 1 to integer'high
			);
	port(
		clk : in std_logic;

		waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);

		be : in std_logic_vector (3 downto 0);
		
		we : in std_logic;

		wdata : in std_logic_vector(31 downto 0);
		
		q : out std_logic_vector(31 downto 0)
	);
	end component r_w_ram_be;

	component ram_xilinx is
	generic	(
				ADDR_WIDTH : integer range 1 to integer'high
			);
	port(
		clk : in std_logic;

		waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);

		be : in std_logic_vector (3 downto 0);
		
		we : in std_logic;

		wdata : in std_logic_vector(31 downto 0);
		
		q : out std_logic_vector(31 downto 0)
	);
	end component ram_xilinx;

	component rom is
	generic	(
				ADDR_WIDTH : integer range 1 to integer'high;
				DATA_WIDTH : integer range 1 to integer'high
			);
	port(
		--System inputs
			clk : in std_logic;
		--Input
			rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);			
		--Output
			data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
		);
	end component rom;
	
	component r2_w_ram is
	generic	(
				ADDR_WIDTH : integer range 1 to integer'high;
				DATA_WIDTH : integer range 1 to integer'high
			);
	port(
		--System inputs
			clk : in std_logic;
		--Input
			wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
			
			wr_en : in std_logic;
			data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
			
		--Output
			data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
		);
	end component r2_w_ram;
	
	component rw_r_ram is
	generic	(
				ADDR_WIDTH : integer range 1 to integer'high;
				DATA_WIDTH : integer range 1 to integer'high
			);
	port(
		--System inputs
			clk : in std_logic;
		--Input
			rw_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
			
			wr_en : in std_logic;
			data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
			
		--Output
			rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
		);
	end component rw_r_ram;

end package mem_pkg;