1 // VGA bios implementation
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
10 // * introduce "struct vregs", or add ebp to struct bregs.
11 // * define structs for save/restore state
12 // * review correctness of converted asm by comparing with RBIL
13 // * refactor redundant code into sub-functions
14 // * See if there is a method to the in/out stuff that can be encapsulated.
15 // * remove "biosfn" prefixes
16 // * verify all funcs static
18 // * convert vbe/clext code
20 // * separate code into separate files
21 // * extract hw code from bios interfaces
23 #include "bregs.h" // struct bregs
24 #include "biosvar.h" // GET_BDA
25 #include "util.h" // memset
26 #include "vgatables.h" // vga_modes
30 #define CONFIG_CIRRUS 0
33 #define DEBUG_VGA_POST 1
34 #define DEBUG_VGA_10 3
36 #define SET_VGA(var, val) SET_FARVAR(get_global_seg(), (var), (val))
39 // ===================================================================
43 // ===================================================================
45 // -------------------------------------------------------------------
47 call16_vgaint(u32 eax, u32 ebx)
60 memcpy16_far(u16 d_seg, void *d_far, u16 s_seg, const void *s_far, size_t len)
62 memcpy_far(d_seg, d_far, s_seg, s_far, len);
66 // ===================================================================
70 // ===================================================================
72 // -------------------------------------------------------------------
74 biosfn_perform_gray_scale_summing(u16 start, u16 count)
76 inb(VGAREG_ACTL_RESET);
77 outb(0x00, VGAREG_ACTL_ADDRESS);
80 for (i = start; i < start+count; i++) {
81 // set read address and switch to read mode
82 outb(i, VGAREG_DAC_READ_ADDRESS);
83 // get 6-bit wide RGB data values
84 u8 r = inb(VGAREG_DAC_DATA);
85 u8 g = inb(VGAREG_DAC_DATA);
86 u8 b = inb(VGAREG_DAC_DATA);
88 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
89 u16 intensity = ((77 * r + 151 * g + 28 * b) + 0x80) >> 8;
94 // set write address and switch to write mode
95 outb(i, VGAREG_DAC_WRITE_ADDRESS);
96 // write new intensity value
97 outb(intensity & 0xff, VGAREG_DAC_DATA);
98 outb(intensity & 0xff, VGAREG_DAC_DATA);
99 outb(intensity & 0xff, VGAREG_DAC_DATA);
101 inb(VGAREG_ACTL_RESET);
102 outb(0x20, VGAREG_ACTL_ADDRESS);
105 // -------------------------------------------------------------------
107 biosfn_set_cursor_shape(u8 CH, u8 CL)
112 u16 curs = (CH << 8) + CL;
113 SET_BDA(cursor_type, curs);
115 u8 modeset_ctl = GET_BDA(modeset_ctl);
116 u16 cheight = GET_BDA(char_height);
117 if ((modeset_ctl & 0x01) && (cheight > 8) && (CL < 8) && (CH < 0x20)) {
119 CH = ((CH + 1) * cheight / 8) - 1;
121 CH = ((CL + 1) * cheight / 8) - 2;
122 CL = ((CL + 1) * cheight / 8) - 1;
124 // CTRC regs 0x0a and 0x0b
125 u16 crtc_addr = GET_BDA(crtc_address);
126 outb(0x0a, crtc_addr);
127 outb(CH, crtc_addr + 1);
128 outb(0x0b, crtc_addr);
129 outb(CL, crtc_addr + 1);
133 biosfn_get_cursor_shape(u8 page)
137 // FIXME should handle VGA 14/16 lines
138 return GET_BDA(cursor_type);
141 // -------------------------------------------------------------------
143 biosfn_set_cursor_pos(u8 page, u16 cursor)
145 // Should not happen...
150 SET_BDA(cursor_pos[page], cursor);
152 // Set the hardware cursor
153 u8 current = GET_BDA(video_page);
157 // Get the dimensions
158 u16 nbcols = GET_BDA(video_cols);
159 u16 nbrows = GET_BDA(video_rows) + 1;
161 u8 xcurs = cursor & 0x00ff;
162 u8 ycurs = (cursor & 0xff00) >> 8;
164 // Calculate the address knowing nbcols nbrows and page num
165 u16 address = SCREEN_IO_START(nbcols, nbrows, page) + xcurs + ycurs * nbcols;
167 // CRTC regs 0x0e and 0x0f
168 u16 crtc_addr = GET_BDA(crtc_address);
169 outb(0x0e, crtc_addr);
170 outb((address & 0xff00) >> 8, crtc_addr + 1);
171 outb(0x0f, crtc_addr);
172 outb(address & 0x00ff, crtc_addr + 1);
176 biosfn_get_cursor_pos(u8 page)
180 // FIXME should handle VGA 14/16 lines
181 return GET_BDA(cursor_pos[page]);
184 // -------------------------------------------------------------------
186 biosfn_set_active_page(u8 page)
192 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
196 // Get pos curs pos for the right page
197 u16 cursor = biosfn_get_cursor_pos(page);
200 if (GET_GLOBAL(vmode_g->class) == TEXT) {
201 // Get the dimensions
202 u16 nbcols = GET_BDA(video_cols);
203 u16 nbrows = GET_BDA(video_rows) + 1;
205 // Calculate the address knowing nbcols nbrows and page num
206 address = SCREEN_MEM_START(nbcols, nbrows, page);
207 SET_BDA(video_pagestart, address);
210 address = SCREEN_IO_START(nbcols, nbrows, page);
212 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
213 address = page * GET_GLOBAL(vparam_g->slength);
216 // CRTC regs 0x0c and 0x0d
217 u16 crtc_addr = GET_BDA(crtc_address);
218 outb(0x0c, crtc_addr);
219 outb((address & 0xff00) >> 8, crtc_addr + 1);
220 outb(0x0d, crtc_addr);
221 outb(address & 0x00ff, crtc_addr + 1);
223 // And change the BIOS page
224 SET_BDA(video_page, page);
226 dprintf(1, "Set active page %02x address %04x\n", page, address);
228 // Display the cursor, now the page is active
229 biosfn_set_cursor_pos(page, cursor);
233 biosfn_set_video_mode(u8 mode)
234 { // mode: Bit 7 is 1 if no clear screen
236 cirrus_set_video_mode(mode);
239 if (vbe_has_vbe_display())
240 dispi_set_enable(VBE_DISPI_DISABLED);
243 u8 noclearmem = mode & 0x80;
246 // find the entry in the video modes
247 struct vgamode_s *vmode_g = find_vga_entry(mode);
248 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
252 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
253 u16 twidth = GET_GLOBAL(vparam_g->twidth);
254 u16 theightm1 = GET_GLOBAL(vparam_g->theightm1);
255 u16 cheight = GET_GLOBAL(vparam_g->cheight);
257 // Read the bios mode set control
258 u8 modeset_ctl = GET_BDA(modeset_ctl);
260 // Then we know the number of lines
263 // if palette loading (bit 3 of modeset ctl = 0)
264 if ((modeset_ctl & 0x08) == 0) { // Set the PEL mask
265 outb(GET_GLOBAL(vmode_g->pelmask), VGAREG_PEL_MASK);
267 // Set the whole dac always, from 0
268 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
270 // From which palette
271 u8 *palette_g = GET_GLOBAL(vmode_g->dac);
272 u16 palsize = GET_GLOBAL(vmode_g->dacsize);
273 // Always 256*3 values
275 for (i = 0; i < 0x0100; i++) {
277 outb(GET_GLOBAL(palette_g[(i * 3) + 0]), VGAREG_DAC_DATA);
278 outb(GET_GLOBAL(palette_g[(i * 3) + 1]), VGAREG_DAC_DATA);
279 outb(GET_GLOBAL(palette_g[(i * 3) + 2]), VGAREG_DAC_DATA);
281 outb(0, VGAREG_DAC_DATA);
282 outb(0, VGAREG_DAC_DATA);
283 outb(0, VGAREG_DAC_DATA);
286 if ((modeset_ctl & 0x02) == 0x02)
287 biosfn_perform_gray_scale_summing(0x00, 0x100);
289 // Reset Attribute Ctl flip-flop
290 inb(VGAREG_ACTL_RESET);
294 for (i = 0; i <= 0x13; i++) {
295 outb(i, VGAREG_ACTL_ADDRESS);
296 outb(GET_GLOBAL(vparam_g->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
298 outb(0x14, VGAREG_ACTL_ADDRESS);
299 outb(0x00, VGAREG_ACTL_WRITE_DATA);
302 outb(0, VGAREG_SEQU_ADDRESS);
303 outb(0x03, VGAREG_SEQU_DATA);
304 for (i = 1; i <= 4; i++) {
305 outb(i, VGAREG_SEQU_ADDRESS);
306 outb(GET_GLOBAL(vparam_g->sequ_regs[i - 1]), VGAREG_SEQU_DATA);
310 for (i = 0; i <= 8; i++) {
311 outb(i, VGAREG_GRDC_ADDRESS);
312 outb(GET_GLOBAL(vparam_g->grdc_regs[i]), VGAREG_GRDC_DATA);
315 // Set CRTC address VGA or MDA
316 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
317 if (GET_GLOBAL(vmode_g->memmodel) == MTEXT)
318 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
320 // Disable CRTC write protection
321 outw(0x0011, crtc_addr);
323 for (i = 0; i <= 0x18; i++) {
325 outb(GET_GLOBAL(vparam_g->crtc_regs[i]), crtc_addr + 1);
328 // Set the misc register
329 outb(GET_GLOBAL(vparam_g->miscreg), VGAREG_WRITE_MISC_OUTPUT);
332 outb(0x20, VGAREG_ACTL_ADDRESS);
333 inb(VGAREG_ACTL_RESET);
335 if (noclearmem == 0x00) {
336 if (GET_GLOBAL(vmode_g->class) == TEXT) {
337 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
340 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
342 outb(0x02, VGAREG_SEQU_ADDRESS);
343 u8 mmask = inb(VGAREG_SEQU_DATA);
344 outb(0x0f, VGAREG_SEQU_DATA); // all planes
345 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
346 outb(mmask, VGAREG_SEQU_DATA);
351 SET_BDA(video_mode, mode);
352 SET_BDA(video_cols, twidth);
353 SET_BDA(video_pagesize, GET_GLOBAL(vparam_g->slength));
354 SET_BDA(crtc_address, crtc_addr);
355 SET_BDA(video_rows, theightm1);
356 SET_BDA(char_height, cheight);
357 SET_BDA(video_ctl, (0x60 | noclearmem));
358 SET_BDA(video_switches, 0xF9);
359 SET_BDA(modeset_ctl, GET_BDA(modeset_ctl) & 0x7f);
361 // FIXME We nearly have the good tables. to be reworked
362 SET_BDA(dcc_index, 0x08); // 8 is VGA should be ok for now
363 SET_BDA(video_savetable_ptr, (u32)video_save_pointer_table);
364 SET_BDA(video_savetable_seg, get_global_seg());
367 SET_BDA(video_msr, 0x00); // Unavailable on vanilla vga, but...
368 SET_BDA(video_pal, 0x00); // Unavailable on vanilla vga, but...
371 if (GET_GLOBAL(vmode_g->class) == TEXT)
372 biosfn_set_cursor_shape(0x06, 0x07);
373 // Set cursor pos for page 0..7
374 for (i = 0; i < 8; i++)
375 biosfn_set_cursor_pos(i, 0x0000);
378 biosfn_set_active_page(0x00);
380 // Write the fonts in memory
381 if (GET_GLOBAL(vmode_g->class) == TEXT) {
382 call16_vgaint(0x1104, 0);
383 call16_vgaint(0x1103, 0);
385 // Set the ints 0x1F and 0x43
386 SET_IVT(0x1f, get_global_seg(), (u32)&vgafont8[128 * 8]);
390 SET_IVT(0x43, get_global_seg(), (u32)vgafont8);
393 SET_IVT(0x43, get_global_seg(), (u32)vgafont14);
396 SET_IVT(0x43, get_global_seg(), (u32)vgafont16);
401 // -------------------------------------------------------------------
403 vgamem_copy_pl4(u8 xstart, u8 ysrc, u8 ydest, u8 cols, u8 nbcols,
406 u16 src = ysrc * cheight * nbcols + xstart;
407 u16 dest = ydest * cheight * nbcols + xstart;
408 outw(0x0105, VGAREG_GRDC_ADDRESS);
410 for (i = 0; i < cheight; i++)
411 memcpy_far(SEG_GRAPH, (void*)(dest + i * nbcols)
412 , SEG_GRAPH, (void*)(src + i * nbcols), cols);
413 outw(0x0005, VGAREG_GRDC_ADDRESS);
416 // -------------------------------------------------------------------
418 vgamem_fill_pl4(u8 xstart, u8 ystart, u8 cols, u8 nbcols, u8 cheight,
421 u16 dest = ystart * cheight * nbcols + xstart;
422 outw(0x0205, VGAREG_GRDC_ADDRESS);
424 for (i = 0; i < cheight; i++)
425 memset_far(SEG_GRAPH, (void*)(dest + i * nbcols), attr, cols);
426 outw(0x0005, VGAREG_GRDC_ADDRESS);
429 // -------------------------------------------------------------------
431 vgamem_copy_cga(u8 xstart, u8 ysrc, u8 ydest, u8 cols, u8 nbcols,
434 u16 src = ((ysrc * cheight * nbcols) >> 1) + xstart;
435 u16 dest = ((ydest * cheight * nbcols) >> 1) + xstart;
437 for (i = 0; i < cheight; i++)
439 memcpy_far(SEG_CTEXT, (void*)(0x2000 + dest + (i >> 1) * nbcols)
440 , SEG_CTEXT, (void*)(0x2000 + src + (i >> 1) * nbcols)
443 memcpy_far(SEG_CTEXT, (void*)(dest + (i >> 1) * nbcols)
444 , SEG_CTEXT, (void*)(src + (i >> 1) * nbcols), cols);
447 // -------------------------------------------------------------------
449 vgamem_fill_cga(u8 xstart, u8 ystart, u8 cols, u8 nbcols, u8 cheight,
452 u16 dest = ((ystart * cheight * nbcols) >> 1) + xstart;
454 for (i = 0; i < cheight; i++)
456 memset_far(SEG_CTEXT, (void*)(0x2000 + dest + (i >> 1) * nbcols)
459 memset_far(SEG_CTEXT, (void*)(dest + (i >> 1) * nbcols), attr, cols);
462 // -------------------------------------------------------------------
464 biosfn_scroll(u8 nblines, u8 attr, u8 rul, u8 cul, u8 rlr, u8 clr, u8 page,
467 // page == 0xFF if current
474 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
478 // Get the dimensions
479 u16 nbrows = GET_BDA(video_rows) + 1;
480 u16 nbcols = GET_BDA(video_cols);
482 // Get the current page
484 page = GET_BDA(video_page);
490 if (nblines > nbrows)
492 u8 cols = clr - cul + 1;
494 if (GET_GLOBAL(vmode_g->class) == TEXT) {
495 // Compute the address
496 void *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page));
497 dprintf(3, "Scroll, address %p (%d %d %02x)\n"
498 , address_far, nbrows, nbcols, page);
500 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
501 && clr == nbcols - 1) {
502 memset16_far(GET_GLOBAL(vmode_g->sstart), address_far
503 , (u16)attr * 0x100 + ' ', nbrows * nbcols * 2);
504 } else { // if Scroll up
505 if (dir == SCROLL_UP) {
507 for (i = rul; i <= rlr; i++)
508 if ((i + nblines > rlr) || (nblines == 0))
509 memset16_far(GET_GLOBAL(vmode_g->sstart)
510 , address_far + (i * nbcols + cul) * 2
511 , (u16)attr * 0x100 + ' ', cols * 2);
513 memcpy16_far(GET_GLOBAL(vmode_g->sstart)
514 , address_far + (i * nbcols + cul) * 2
515 , GET_GLOBAL(vmode_g->sstart)
516 , (void*)(((i + nblines) * nbcols + cul) * 2)
520 for (i = rlr; i >= rul; i--) {
521 if ((i < rul + nblines) || (nblines == 0))
522 memset16_far(GET_GLOBAL(vmode_g->sstart)
523 , address_far + (i * nbcols + cul) * 2
524 , (u16)attr * 0x100 + ' ', cols * 2);
526 memcpy16_far(GET_GLOBAL(vmode_g->sstart)
527 , address_far + (i * nbcols + cul) * 2
528 , GET_GLOBAL(vmode_g->sstart)
529 , (void*)(((i - nblines) * nbcols + cul) * 2)
539 // FIXME gfx mode not complete
540 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
541 u8 cheight = GET_GLOBAL(vparam_g->cheight);
542 switch (GET_GLOBAL(vmode_g->memmodel)) {
545 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
546 && clr == nbcols - 1) {
547 outw(0x0205, VGAREG_GRDC_ADDRESS);
548 memset_far(GET_GLOBAL(vmode_g->sstart), 0, attr,
549 nbrows * nbcols * cheight);
550 outw(0x0005, VGAREG_GRDC_ADDRESS);
551 } else { // if Scroll up
552 if (dir == SCROLL_UP) {
554 for (i = rul; i <= rlr; i++)
555 if ((i + nblines > rlr) || (nblines == 0))
556 vgamem_fill_pl4(cul, i, cols, nbcols, cheight,
559 vgamem_copy_pl4(cul, i + nblines, i, cols,
563 for (i = rlr; i >= rul; i--) {
564 if ((i < rul + nblines) || (nblines == 0))
565 vgamem_fill_pl4(cul, i, cols, nbcols, cheight,
568 vgamem_copy_pl4(cul, i, i - nblines, cols,
577 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
578 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
579 && clr == nbcols - 1) {
580 memset_far(GET_GLOBAL(vmode_g->sstart), 0, attr,
581 nbrows * nbcols * cheight * bpp);
589 if (dir == SCROLL_UP) {
591 for (i = rul; i <= rlr; i++)
592 if ((i + nblines > rlr) || (nblines == 0))
593 vgamem_fill_cga(cul, i, cols, nbcols, cheight,
596 vgamem_copy_cga(cul, i + nblines, i, cols,
600 for (i = rlr; i >= rul; i--) {
601 if ((i < rul + nblines) || (nblines == 0))
602 vgamem_fill_cga(cul, i, cols, nbcols, cheight,
605 vgamem_copy_cga(cul, i, i - nblines, cols,
615 dprintf(1, "Scroll in graphics mode\n");
619 // -------------------------------------------------------------------
621 biosfn_read_char_attr(u8 page, u16 *car)
624 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
628 // Get the cursor pos for the page
629 u16 cursor = biosfn_get_cursor_pos(page);
630 u8 xcurs = cursor & 0x00ff;
631 u8 ycurs = (cursor & 0xff00) >> 8;
633 // Get the dimensions
634 u16 nbrows = GET_BDA(video_rows) + 1;
635 u16 nbcols = GET_BDA(video_cols);
637 if (GET_GLOBAL(vmode_g->class) == TEXT) {
638 // Compute the address
639 u16 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
640 + (xcurs + ycurs * nbcols) * 2);
642 *car = GET_FARVAR(GET_GLOBAL(vmode_g->sstart), *address_far);
645 dprintf(1, "Read char in graphics mode\n");
649 // -------------------------------------------------------------------
651 write_gfx_char_pl4(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols,
665 u16 addr = xcurs + ycurs * cheight * nbcols;
666 u16 src = car * cheight;
667 outw(0x0f02, VGAREG_SEQU_ADDRESS);
668 outw(0x0205, VGAREG_GRDC_ADDRESS);
670 outw(0x1803, VGAREG_GRDC_ADDRESS);
672 outw(0x0003, VGAREG_GRDC_ADDRESS);
674 for (i = 0; i < cheight; i++) {
675 u8 *dest_far = (void*)(addr + i * nbcols);
677 for (j = 0; j < 8; j++) {
679 outw((mask << 8) | 0x08, VGAREG_GRDC_ADDRESS);
680 GET_FARVAR(SEG_GRAPH, *dest_far);
681 if (GET_GLOBAL(fdata_g[src + i]) & mask)
682 SET_FARVAR(SEG_GRAPH, *dest_far, attr & 0x0f);
684 SET_FARVAR(SEG_GRAPH, *dest_far, 0x00);
687 outw(0xff08, VGAREG_GRDC_ADDRESS);
688 outw(0x0005, VGAREG_GRDC_ADDRESS);
689 outw(0x0003, VGAREG_GRDC_ADDRESS);
692 // -------------------------------------------------------------------
694 write_gfx_char_cga(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols, u8 bpp)
696 u8 *fdata_g = vgafont8;
697 u16 addr = (xcurs * bpp) + ycurs * 320;
700 for (i = 0; i < 8; i++) {
701 u8 *dest_far = (void*)(addr + (i >> 1) * 80);
708 data = GET_FARVAR(SEG_CTEXT, *dest_far);
710 for (j = 0; j < 8; j++) {
711 if (GET_GLOBAL(fdata_g[src + i]) & mask) {
713 data ^= (attr & 0x01) << (7 - j);
715 data |= (attr & 0x01) << (7 - j);
719 SET_FARVAR(SEG_CTEXT, *dest_far, data);
724 data = GET_FARVAR(SEG_CTEXT, *dest_far);
726 for (j = 0; j < 4; j++) {
727 if (GET_GLOBAL(fdata_g[src + i]) & mask) {
729 data ^= (attr & 0x03) << ((3 - j) * 2);
731 data |= (attr & 0x03) << ((3 - j) * 2);
735 SET_FARVAR(SEG_CTEXT, *dest_far, data);
742 // -------------------------------------------------------------------
744 write_gfx_char_lin(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols)
746 u8 *fdata_g = vgafont8;
747 u16 addr = xcurs * 8 + ycurs * nbcols * 64;
750 for (i = 0; i < 8; i++) {
751 u8 *dest_far = (void*)(addr + i * nbcols * 8);
754 for (j = 0; j < 8; j++) {
756 if (GET_GLOBAL(fdata_g[src + i]) & mask)
758 SET_FARVAR(SEG_GRAPH, dest_far[j], data);
764 // -------------------------------------------------------------------
766 biosfn_write_char_attr(u8 car, u8 page, u8 attr, u16 count)
769 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
773 // Get the cursor pos for the page
774 u16 cursor = biosfn_get_cursor_pos(page);
775 u8 xcurs = cursor & 0x00ff;
776 u8 ycurs = (cursor & 0xff00) >> 8;
778 // Get the dimensions
779 u16 nbrows = GET_BDA(video_rows) + 1;
780 u16 nbcols = GET_BDA(video_cols);
782 if (GET_GLOBAL(vmode_g->class) == TEXT) {
783 // Compute the address
784 void *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
785 + (xcurs + ycurs * nbcols) * 2);
787 u16 dummy = ((u16)attr << 8) + car;
788 memset16_far(GET_GLOBAL(vmode_g->sstart), address_far, dummy, count * 2);
792 // FIXME gfx mode not complete
793 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
794 u8 cheight = GET_GLOBAL(vparam_g->cheight);
795 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
796 while ((count-- > 0) && (xcurs < nbcols)) {
797 switch (GET_GLOBAL(vmode_g->memmodel)) {
800 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
804 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
807 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
814 // -------------------------------------------------------------------
816 biosfn_write_char_only(u8 car, u8 page, u8 attr, u16 count)
819 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
823 // Get the cursor pos for the page
824 u16 cursor = biosfn_get_cursor_pos(page);
825 u8 xcurs = cursor & 0x00ff;
826 u8 ycurs = (cursor & 0xff00) >> 8;
828 // Get the dimensions
829 u16 nbrows = GET_BDA(video_rows) + 1;
830 u16 nbcols = GET_BDA(video_cols);
832 if (GET_GLOBAL(vmode_g->class) == TEXT) {
833 // Compute the address
834 u8 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
835 + (xcurs + ycurs * nbcols) * 2);
836 while (count-- > 0) {
837 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), *address_far, car);
843 // FIXME gfx mode not complete
844 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
845 u8 cheight = GET_GLOBAL(vparam_g->cheight);
846 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
847 while ((count-- > 0) && (xcurs < nbcols)) {
848 switch (GET_GLOBAL(vmode_g->memmodel)) {
851 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
855 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
858 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
865 // -------------------------------------------------------------------
867 biosfn_set_border_color(struct bregs *regs)
869 inb(VGAREG_ACTL_RESET);
870 outb(0x00, VGAREG_ACTL_ADDRESS);
871 u8 al = regs->bl & 0x0f;
874 outb(al, VGAREG_ACTL_WRITE_DATA);
875 u8 bl = regs->bl & 0x10;
878 for (i = 1; i < 4; i++) {
879 outb(i, VGAREG_ACTL_ADDRESS);
881 al = inb(VGAREG_ACTL_READ_DATA);
884 outb(al, VGAREG_ACTL_WRITE_DATA);
886 outb(0x20, VGAREG_ACTL_ADDRESS);
890 biosfn_set_palette(struct bregs *regs)
892 inb(VGAREG_ACTL_RESET);
893 u8 bl = regs->bl & 0x01;
895 for (i = 1; i < 4; i++) {
896 outb(i, VGAREG_ACTL_ADDRESS);
898 u8 al = inb(VGAREG_ACTL_READ_DATA);
901 outb(al, VGAREG_ACTL_WRITE_DATA);
903 outb(0x20, VGAREG_ACTL_ADDRESS);
906 // -------------------------------------------------------------------
908 biosfn_write_pixel(u8 BH, u8 AL, u16 CX, u16 DX)
911 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
914 if (GET_GLOBAL(vmode_g->class) == TEXT)
917 u8 *addr_far, mask, attr, data;
918 switch (GET_GLOBAL(vmode_g->memmodel)) {
921 addr_far = (void*)(CX / 8 + DX * GET_BDA(video_cols));
922 mask = 0x80 >> (CX & 0x07);
923 outw((mask << 8) | 0x08, VGAREG_GRDC_ADDRESS);
924 outw(0x0205, VGAREG_GRDC_ADDRESS);
925 data = GET_FARVAR(SEG_GRAPH, *addr_far);
927 outw(0x1803, VGAREG_GRDC_ADDRESS);
928 SET_FARVAR(SEG_GRAPH, *addr_far, AL);
929 outw(0xff08, VGAREG_GRDC_ADDRESS);
930 outw(0x0005, VGAREG_GRDC_ADDRESS);
931 outw(0x0003, VGAREG_GRDC_ADDRESS);
934 if (GET_GLOBAL(vmode_g->pixbits) == 2)
935 addr_far = (void*)((CX >> 2) + (DX >> 1) * 80);
937 addr_far = (void*)((CX >> 3) + (DX >> 1) * 80);
940 data = GET_FARVAR(SEG_CTEXT, *addr_far);
941 if (GET_GLOBAL(vmode_g->pixbits) == 2) {
942 attr = (AL & 0x03) << ((3 - (CX & 0x03)) * 2);
943 mask = 0x03 << ((3 - (CX & 0x03)) * 2);
945 attr = (AL & 0x01) << (7 - (CX & 0x07));
946 mask = 0x01 << (7 - (CX & 0x07));
954 SET_FARVAR(SEG_CTEXT, *addr_far, data);
957 addr_far = (void*)(CX + DX * (GET_BDA(video_cols) * 8));
958 SET_FARVAR(SEG_GRAPH, *addr_far, AL);
963 // -------------------------------------------------------------------
965 biosfn_read_pixel(u8 BH, u16 CX, u16 DX, u16 *AX)
968 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
971 if (GET_GLOBAL(vmode_g->class) == TEXT)
974 u8 *addr_far, mask, attr=0, data, i;
975 switch (GET_GLOBAL(vmode_g->memmodel)) {
978 addr_far = (void*)(CX / 8 + DX * GET_BDA(video_cols));
979 mask = 0x80 >> (CX & 0x07);
981 for (i = 0; i < 4; i++) {
982 outw((i << 8) | 0x04, VGAREG_GRDC_ADDRESS);
983 data = GET_FARVAR(SEG_GRAPH, *addr_far) & mask;
989 addr_far = (void*)((CX >> 2) + (DX >> 1) * 80);
992 data = GET_FARVAR(SEG_CTEXT, *addr_far);
993 if (GET_GLOBAL(vmode_g->pixbits) == 2)
994 attr = (data >> ((3 - (CX & 0x03)) * 2)) & 0x03;
996 attr = (data >> (7 - (CX & 0x07))) & 0x01;
999 addr_far = (void*)(CX + DX * (GET_BDA(video_cols) * 8));
1000 attr = GET_FARVAR(SEG_GRAPH, *addr_far);
1003 *AX = (*AX & 0xff00) | attr;
1006 // -------------------------------------------------------------------
1008 biosfn_write_teletype(u8 car, u8 page, u8 attr, u8 flag)
1009 { // flag = WITH_ATTR / NO_ATTR
1010 // special case if page is 0xff, use current page
1012 page = GET_BDA(video_page);
1015 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
1019 // Get the cursor pos for the page
1020 u16 cursor = biosfn_get_cursor_pos(page);
1021 u8 xcurs = cursor & 0x00ff;
1022 u8 ycurs = (cursor & 0xff00) >> 8;
1024 // Get the dimensions
1025 u16 nbrows = GET_BDA(video_rows) + 1;
1026 u16 nbcols = GET_BDA(video_cols);
1048 biosfn_write_teletype(' ', page, attr, flag);
1049 cursor = biosfn_get_cursor_pos(page);
1050 xcurs = cursor & 0x00ff;
1051 ycurs = (cursor & 0xff00) >> 8;
1052 } while (xcurs % 8 == 0);
1057 if (GET_GLOBAL(vmode_g->class) == TEXT) {
1058 // Compute the address
1059 u8 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
1060 + (xcurs + ycurs * nbcols) * 2);
1062 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), address_far[0], car);
1063 if (flag == WITH_ATTR)
1064 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), address_far[1], attr);
1066 // FIXME gfx mode not complete
1067 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
1068 u8 cheight = GET_GLOBAL(vparam_g->cheight);
1069 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
1070 switch (GET_GLOBAL(vmode_g->memmodel)) {
1073 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols, cheight);
1076 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
1079 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
1086 // Do we need to wrap ?
1087 if (xcurs == nbcols) {
1091 // Do we need to scroll ?
1092 if (ycurs == nbrows) {
1093 if (GET_GLOBAL(vmode_g->class) == TEXT)
1094 biosfn_scroll(0x01, 0x07, 0, 0, nbrows - 1, nbcols - 1, page,
1097 biosfn_scroll(0x01, 0x00, 0, 0, nbrows - 1, nbcols - 1, page,
1101 // Set the cursor for the page
1105 biosfn_set_cursor_pos(page, cursor);
1108 // -------------------------------------------------------------------
1110 biosfn_get_video_mode(struct bregs *regs)
1112 regs->bh = GET_BDA(video_page);
1113 regs->al = GET_BDA(video_mode) | (GET_BDA(video_ctl) & 0x80);
1114 regs->ah = GET_BDA(video_cols);
1117 // -------------------------------------------------------------------
1119 biosfn_set_overscan_border_color(struct bregs *regs)
1121 inb(VGAREG_ACTL_RESET);
1122 outb(0x11, VGAREG_ACTL_ADDRESS);
1123 outb(regs->bh, VGAREG_ACTL_WRITE_DATA);
1124 outb(0x20, VGAREG_ACTL_ADDRESS);
1127 // -------------------------------------------------------------------
1129 biosfn_set_all_palette_reg(struct bregs *regs)
1131 inb(VGAREG_ACTL_RESET);
1133 u8 *data_far = (u8*)(regs->dx + 0);
1135 for (i = 0; i < 0x10; i++) {
1136 outb(i, VGAREG_ACTL_ADDRESS);
1137 u8 val = GET_FARVAR(regs->es, *data_far);
1138 outb(val, VGAREG_ACTL_WRITE_DATA);
1141 outb(0x11, VGAREG_ACTL_ADDRESS);
1142 outb(GET_FARVAR(regs->es, *data_far), VGAREG_ACTL_WRITE_DATA);
1143 outb(0x20, VGAREG_ACTL_ADDRESS);
1146 // -------------------------------------------------------------------
1148 biosfn_toggle_intensity(struct bregs *regs)
1150 inb(VGAREG_ACTL_RESET);
1151 outb(0x10, VGAREG_ACTL_ADDRESS);
1152 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0x7f) | ((regs->bl & 0x01) << 3);
1153 outb(val, VGAREG_ACTL_WRITE_DATA);
1154 outb(0x20, VGAREG_ACTL_ADDRESS);
1157 // -------------------------------------------------------------------
1159 biosfn_set_single_palette_reg(u8 reg, u8 val)
1161 inb(VGAREG_ACTL_RESET);
1162 outb(reg, VGAREG_ACTL_ADDRESS);
1163 outb(val, VGAREG_ACTL_WRITE_DATA);
1164 outb(0x20, VGAREG_ACTL_ADDRESS);
1167 // -------------------------------------------------------------------
1169 biosfn_get_single_palette_reg(u8 reg)
1171 inb(VGAREG_ACTL_RESET);
1172 outb(reg, VGAREG_ACTL_ADDRESS);
1173 u8 v = inb(VGAREG_ACTL_READ_DATA);
1174 inb(VGAREG_ACTL_RESET);
1175 outb(0x20, VGAREG_ACTL_ADDRESS);
1179 // -------------------------------------------------------------------
1181 biosfn_read_overscan_border_color(struct bregs *regs)
1183 inb(VGAREG_ACTL_RESET);
1184 outb(0x11, VGAREG_ACTL_ADDRESS);
1185 regs->bh = inb(VGAREG_ACTL_READ_DATA);
1186 inb(VGAREG_ACTL_RESET);
1187 outb(0x20, VGAREG_ACTL_ADDRESS);
1190 // -------------------------------------------------------------------
1192 biosfn_get_all_palette_reg(struct bregs *regs)
1194 u8 *data_far = (u8*)(regs->dx + 0);
1196 for (i = 0; i < 0x10; i++) {
1197 inb(VGAREG_ACTL_RESET);
1198 outb(i, VGAREG_ACTL_ADDRESS);
1199 SET_FARVAR(regs->es, *data_far, inb(VGAREG_ACTL_READ_DATA));
1202 inb(VGAREG_ACTL_RESET);
1203 outb(0x11, VGAREG_ACTL_ADDRESS);
1204 SET_FARVAR(regs->es, *data_far, inb(VGAREG_ACTL_READ_DATA));
1205 inb(VGAREG_ACTL_RESET);
1206 outb(0x20, VGAREG_ACTL_ADDRESS);
1209 // -------------------------------------------------------------------
1211 biosfn_set_single_dac_reg(struct bregs *regs)
1213 outb(regs->bl, VGAREG_DAC_WRITE_ADDRESS);
1214 outb(regs->dh, VGAREG_DAC_DATA);
1215 outb(regs->ch, VGAREG_DAC_DATA);
1216 outb(regs->cl, VGAREG_DAC_DATA);
1219 // -------------------------------------------------------------------
1221 biosfn_set_all_dac_reg(struct bregs *regs)
1223 outb(regs->bl, VGAREG_DAC_WRITE_ADDRESS);
1224 u8 *data_far = (u8*)(regs->dx + 0);
1225 int count = regs->cx;
1227 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1229 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1231 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1237 // -------------------------------------------------------------------
1239 biosfn_select_video_dac_color_page(struct bregs *regs)
1241 inb(VGAREG_ACTL_RESET);
1242 outb(0x10, VGAREG_ACTL_ADDRESS);
1243 u8 val = inb(VGAREG_ACTL_READ_DATA);
1244 if (!(regs->bl & 0x01)) {
1245 val = (val & 0x7f) | (regs->bh << 7);
1246 outb(val, VGAREG_ACTL_WRITE_DATA);
1247 outb(0x20, VGAREG_ACTL_ADDRESS);
1250 inb(VGAREG_ACTL_RESET);
1251 outb(0x14, VGAREG_ACTL_ADDRESS);
1256 outb(bh, VGAREG_ACTL_WRITE_DATA);
1257 outb(0x20, VGAREG_ACTL_ADDRESS);
1260 // -------------------------------------------------------------------
1262 biosfn_read_single_dac_reg(struct bregs *regs)
1264 outb(regs->bl, VGAREG_DAC_READ_ADDRESS);
1265 regs->dh = inb(VGAREG_DAC_DATA);
1266 regs->ch = inb(VGAREG_DAC_DATA);
1267 regs->cl = inb(VGAREG_DAC_DATA);
1270 // -------------------------------------------------------------------
1272 biosfn_read_all_dac_reg(struct bregs *regs)
1274 outb(regs->bl, VGAREG_DAC_READ_ADDRESS);
1275 u8 *data_far = (u8*)(regs->dx + 0);
1276 int count = regs->cx;
1278 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1280 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1282 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1288 // -------------------------------------------------------------------
1290 biosfn_set_pel_mask(struct bregs *regs)
1292 outb(regs->bl, VGAREG_PEL_MASK);
1295 // -------------------------------------------------------------------
1297 biosfn_read_pel_mask(struct bregs *regs)
1299 regs->bl = inb(VGAREG_PEL_MASK);
1302 // -------------------------------------------------------------------
1304 biosfn_read_video_dac_state(struct bregs *regs)
1306 inb(VGAREG_ACTL_RESET);
1307 outb(0x10, VGAREG_ACTL_ADDRESS);
1308 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
1310 inb(VGAREG_ACTL_RESET);
1311 outb(0x14, VGAREG_ACTL_ADDRESS);
1312 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
1316 inb(VGAREG_ACTL_RESET);
1317 outb(0x20, VGAREG_ACTL_ADDRESS);
1323 // -------------------------------------------------------------------
1327 outw(0x0100, VGAREG_SEQU_ADDRESS);
1328 outw(0x0402, VGAREG_SEQU_ADDRESS);
1329 outw(0x0704, VGAREG_SEQU_ADDRESS);
1330 outw(0x0300, VGAREG_SEQU_ADDRESS);
1331 outw(0x0204, VGAREG_GRDC_ADDRESS);
1332 outw(0x0005, VGAREG_GRDC_ADDRESS);
1333 outw(0x0406, VGAREG_GRDC_ADDRESS);
1337 release_font_access()
1339 outw(0x0100, VGAREG_SEQU_ADDRESS);
1340 outw(0x0302, VGAREG_SEQU_ADDRESS);
1341 outw(0x0304, VGAREG_SEQU_ADDRESS);
1342 outw(0x0300, VGAREG_SEQU_ADDRESS);
1343 u16 v = inw(VGAREG_READ_MISC_OUTPUT);
1344 v = ((v & 0x01) << 10) | 0x0a06;
1345 outw(v, VGAREG_GRDC_ADDRESS);
1346 outw(0x0004, VGAREG_GRDC_ADDRESS);
1347 outw(0x1005, VGAREG_GRDC_ADDRESS);
1351 set_scan_lines(u8 lines)
1353 u16 crtc_addr = GET_BDA(crtc_address);
1354 outb(0x09, crtc_addr);
1355 u8 crtc_r9 = inb(crtc_addr + 1);
1356 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
1357 outb(crtc_r9, crtc_addr + 1);
1359 biosfn_set_cursor_shape(0x06, 0x07);
1361 biosfn_set_cursor_shape(lines - 4, lines - 3);
1362 SET_BDA(char_height, lines);
1363 outb(0x12, crtc_addr);
1364 u16 vde = inb(crtc_addr + 1);
1365 outb(0x07, crtc_addr);
1366 u8 ovl = inb(crtc_addr + 1);
1367 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
1368 u8 rows = vde / lines;
1369 SET_BDA(video_rows, rows - 1);
1370 u16 cols = GET_BDA(video_cols);
1371 SET_BDA(video_pagesize, rows * cols * 2);
1375 biosfn_load_text_user_pat(u8 AL, u16 ES, u16 BP, u16 CX, u16 DX, u8 BL,
1379 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1381 for (i = 0; i < CX; i++) {
1382 void *src_far = (void*)(BP + i * BH);
1383 void *dest_far = (void*)(blockaddr + (DX + i) * 32);
1384 memcpy_far(SEG_GRAPH, dest_far, ES, src_far, BH);
1386 release_font_access();
1392 biosfn_load_text_8_14_pat(u8 AL, u8 BL)
1395 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1397 for (i = 0; i < 0x100; i++) {
1399 void *dest_far = (void*)(blockaddr + i * 32);
1400 memcpy_far(SEG_GRAPH, dest_far, get_global_seg(), &vgafont14[src], 14);
1402 release_font_access();
1408 biosfn_load_text_8_8_pat(u8 AL, u8 BL)
1411 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1413 for (i = 0; i < 0x100; i++) {
1415 void *dest_far = (void*)(blockaddr + i * 32);
1416 memcpy_far(SEG_GRAPH, dest_far, get_global_seg(), &vgafont8[src], 8);
1418 release_font_access();
1423 // -------------------------------------------------------------------
1425 biosfn_set_text_block_specifier(struct bregs *regs)
1427 outw((regs->bl << 8) | 0x03, VGAREG_SEQU_ADDRESS);
1430 // -------------------------------------------------------------------
1432 biosfn_load_text_8_16_pat(u8 AL, u8 BL)
1435 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1437 for (i = 0; i < 0x100; i++) {
1439 void *dest_far = (void*)(blockaddr + i * 32);
1440 memcpy_far(SEG_GRAPH, dest_far, get_global_seg(), &vgafont16[src], 16);
1442 release_font_access();
1447 // -------------------------------------------------------------------
1449 biosfn_get_font_info(u8 BH, u16 *ES, u16 *BP, u16 *CX, u16 *DX)
1453 u32 segoff = GET_IVT(0x1f).segoff;
1459 u32 segoff = GET_IVT(0x43).segoff;
1465 *ES = get_global_seg();
1466 *BP = (u32)vgafont14;
1469 *ES = get_global_seg();
1470 *BP = (u32)vgafont8;
1473 *ES = get_global_seg();
1474 *BP = (u32)vgafont8 + 128 * 8;
1477 *ES = get_global_seg();
1478 *BP = (u32)vgafont14alt;
1481 *ES = get_global_seg();
1482 *BP = (u32)vgafont16;
1485 *ES = get_global_seg();
1486 *BP = (u32)vgafont16alt;
1489 dprintf(1, "Get font info BH(%02x) was discarded\n", BH);
1492 // Set byte/char of on screen font
1493 *CX = GET_BDA(char_height) & 0xff;
1495 // Set Highest char row
1496 *DX = GET_BDA(video_rows);
1499 // -------------------------------------------------------------------
1501 biosfn_get_ega_info(struct bregs *regs)
1503 regs->cx = GET_BDA(video_switches) & 0x0f;
1504 regs->ax = GET_BDA(crtc_address);
1505 if (regs->ax == VGAREG_MDA_CRTC_ADDRESS)
1511 // -------------------------------------------------------------------
1513 biosfn_select_vert_res(struct bregs *regs)
1515 u8 mctl = GET_BDA(modeset_ctl);
1516 u8 vswt = GET_BDA(video_switches);
1521 mctl = (mctl & ~0x10) | 0x80;
1522 vswt = (vswt & ~0x0f) | 0x08;
1527 vswt = (vswt & ~0x0f) | 0x09;
1531 mctl = (mctl & ~0x80) | 0x10;
1532 vswt = (vswt & ~0x0f) | 0x09;
1535 dprintf(1, "Select vert res (%02x) was discarded\n", regs->al);
1538 SET_BDA(modeset_ctl, mctl);
1539 SET_BDA(video_switches, vswt);
1544 biosfn_enable_default_palette_loading(struct bregs *regs)
1546 u8 v = (regs->al & 0x01) << 3;
1547 u8 mctl = GET_BDA(video_ctl) & ~0x08;
1548 SET_BDA(video_ctl, mctl | v);
1553 biosfn_enable_video_addressing(struct bregs *regs)
1555 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1556 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
1557 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
1563 biosfn_enable_grayscale_summing(struct bregs *regs)
1565 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1566 u8 v2 = GET_BDA(modeset_ctl) & ~0x02;
1567 SET_BDA(modeset_ctl, v | v2);
1572 biosfn_enable_cursor_emulation(struct bregs *regs)
1574 u8 v = (regs->al & 0x01) ^ 0x01;
1575 u8 v2 = GET_BDA(modeset_ctl) & ~0x01;
1576 SET_BDA(modeset_ctl, v | v2);
1580 // -------------------------------------------------------------------
1582 biosfn_write_string(u8 flag, u8 page, u8 attr, u16 count, u8 row, u8 col,
1583 u16 seg, u8 *offset_far)
1585 // Read curs info for the page
1586 u16 oldcurs = biosfn_get_cursor_pos(page);
1588 // if row=0xff special case : use current cursor position
1590 col = oldcurs & 0x00ff;
1591 row = (oldcurs & 0xff00) >> 8;
1597 biosfn_set_cursor_pos(page, newcurs);
1599 while (count-- != 0) {
1600 u8 car = GET_FARVAR(seg, *offset_far);
1602 if ((flag & 0x02) != 0) {
1603 attr = GET_FARVAR(seg, *offset_far);
1607 biosfn_write_teletype(car, page, attr, WITH_ATTR);
1610 // Set back curs pos
1611 if ((flag & 0x01) == 0)
1612 biosfn_set_cursor_pos(page, oldcurs);
1615 // -------------------------------------------------------------------
1617 biosfn_read_display_code(struct bregs *regs)
1619 regs->bx = GET_BDA(dcc_index);
1624 biosfn_set_display_code(struct bregs *regs)
1626 SET_BDA(dcc_index, regs->bl);
1627 dprintf(1, "Alternate Display code (%02x) was discarded\n", regs->bh);
1631 // -------------------------------------------------------------------
1633 biosfn_read_state_info(u16 BX, u16 ES, u16 DI)
1635 // Address of static functionality table
1636 SET_FARVAR(ES, *(u16*)(DI + 0x00), (u32)static_functionality);
1637 SET_FARVAR(ES, *(u16*)(DI + 0x02), get_global_seg());
1639 // Hard coded copy from BIOS area. Should it be cleaner ?
1640 memcpy_far(ES, (void*)(DI + 0x04), SEG_BDA, (void*)0x49, 30);
1641 memcpy_far(ES, (void*)(DI + 0x22), SEG_BDA, (void*)0x84, 3);
1643 SET_FARVAR(ES, *(u8*)(DI + 0x25), GET_BDA(dcc_index));
1644 SET_FARVAR(ES, *(u8*)(DI + 0x26), 0);
1645 SET_FARVAR(ES, *(u8*)(DI + 0x27), 16);
1646 SET_FARVAR(ES, *(u8*)(DI + 0x28), 0);
1647 SET_FARVAR(ES, *(u8*)(DI + 0x29), 8);
1648 SET_FARVAR(ES, *(u8*)(DI + 0x2a), 2);
1649 SET_FARVAR(ES, *(u8*)(DI + 0x2b), 0);
1650 SET_FARVAR(ES, *(u8*)(DI + 0x2c), 0);
1651 SET_FARVAR(ES, *(u8*)(DI + 0x31), 3);
1652 SET_FARVAR(ES, *(u8*)(DI + 0x32), 0);
1654 memset_far(ES, (void*)(DI + 0x33), 0, 13);
1657 // -------------------------------------------------------------------
1658 // -------------------------------------------------------------------
1660 biosfn_read_video_state_size(u16 CX)
1666 size += (5 + 8 + 5) * 2 + 6;
1668 size += 3 + 256 * 3 + 1;
1673 biosfn_save_video_state(u16 CX, u16 ES, u16 BX)
1675 u16 crtc_addr = GET_BDA(crtc_address);
1677 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_ADDRESS));
1679 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr));
1681 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_ADDRESS));
1683 inb(VGAREG_ACTL_RESET);
1684 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
1685 SET_FARVAR(ES, *(u8*)(BX+0), ar_index);
1687 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_READ_FEATURE_CTL));
1691 for (i = 1; i <= 4; i++) {
1692 outb(i, VGAREG_SEQU_ADDRESS);
1693 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
1696 outb(0, VGAREG_SEQU_ADDRESS);
1697 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
1700 for (i = 0; i <= 0x18; i++) {
1702 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr + 1));
1706 for (i = 0; i <= 0x13; i++) {
1707 inb(VGAREG_ACTL_RESET);
1708 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
1709 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_ACTL_READ_DATA));
1712 inb(VGAREG_ACTL_RESET);
1714 for (i = 0; i <= 8; i++) {
1715 outb(i, VGAREG_GRDC_ADDRESS);
1716 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_DATA));
1720 SET_FARVAR(ES, *(u16*)(BX+0), crtc_addr);
1723 /* XXX: read plane latches */
1724 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1726 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1728 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1730 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1734 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_mode));
1736 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_cols));
1738 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagesize));
1740 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(crtc_address));
1742 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_rows));
1744 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(char_height));
1746 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_ctl));
1748 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_switches));
1750 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(modeset_ctl));
1752 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_type));
1755 for (i = 0; i < 8; i++) {
1756 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_pos[i]));
1759 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagestart));
1761 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_page));
1764 SET_FARVAR(ES, *(u32*)(BX+0), GET_IVT(0x1f).segoff);
1766 SET_FARVAR(ES, *(u32*)(BX+0), GET_IVT(0x43).segoff);
1770 /* XXX: check this */
1771 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_STATE));
1772 BX++; /* read/write mode dac */
1773 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_WRITE_ADDRESS));
1774 BX++; /* pix address */
1775 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_PEL_MASK));
1777 // Set the whole dac always, from 0
1778 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
1780 for (i = 0; i < 256 * 3; i++) {
1781 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_DATA));
1784 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1785 BX++; /* color select register */
1791 biosfn_restore_video_state(u16 CX, u16 ES, u16 BX)
1794 // Reset Attribute Ctl flip-flop
1795 inb(VGAREG_ACTL_RESET);
1797 u16 crtc_addr = GET_FARVAR(ES, *(u16*)(BX + 0x40));
1802 for (i = 1; i <= 4; i++) {
1803 outb(i, VGAREG_SEQU_ADDRESS);
1804 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
1807 outb(0, VGAREG_SEQU_ADDRESS);
1808 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
1811 // Disable CRTC write protection
1812 outw(0x0011, crtc_addr);
1814 for (i = 0; i <= 0x18; i++) {
1817 outb(GET_FARVAR(ES, *(u8*)(BX+0)), crtc_addr + 1);
1821 // select crtc base address
1822 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
1823 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
1825 outb(v, VGAREG_WRITE_MISC_OUTPUT);
1827 // enable write protection if needed
1828 outb(0x11, crtc_addr);
1829 outb(GET_FARVAR(ES, *(u8*)(BX - 0x18 + 0x11)), crtc_addr + 1);
1831 // Set Attribute Ctl
1832 u16 ar_index = GET_FARVAR(ES, *(u8*)(addr1 + 0x03));
1833 inb(VGAREG_ACTL_RESET);
1834 for (i = 0; i <= 0x13; i++) {
1835 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
1836 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_ACTL_WRITE_DATA);
1839 outb(ar_index, VGAREG_ACTL_ADDRESS);
1840 inb(VGAREG_ACTL_RESET);
1842 for (i = 0; i <= 8; i++) {
1843 outb(i, VGAREG_GRDC_ADDRESS);
1844 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_GRDC_DATA);
1847 BX += 2; /* crtc_addr */
1848 BX += 4; /* plane latches */
1850 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_SEQU_ADDRESS);
1852 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr);
1854 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_GRDC_ADDRESS);
1857 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr - 0x4 + 0xa);
1861 SET_BDA(video_mode, GET_FARVAR(ES, *(u8*)(BX+0)));
1863 SET_BDA(video_cols, GET_FARVAR(ES, *(u16*)(BX+0)));
1865 SET_BDA(video_pagesize, GET_FARVAR(ES, *(u16*)(BX+0)));
1867 SET_BDA(crtc_address, GET_FARVAR(ES, *(u16*)(BX+0)));
1869 SET_BDA(video_rows, GET_FARVAR(ES, *(u8*)(BX+0)));
1871 SET_BDA(char_height, GET_FARVAR(ES, *(u16*)(BX+0)));
1873 SET_BDA(video_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
1875 SET_BDA(video_switches, GET_FARVAR(ES, *(u8*)(BX+0)));
1877 SET_BDA(modeset_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
1879 SET_BDA(cursor_type, GET_FARVAR(ES, *(u16*)(BX+0)));
1882 for (i = 0; i < 8; i++) {
1883 SET_BDA(cursor_pos[i], GET_FARVAR(ES, *(u16*)(BX+0)));
1886 SET_BDA(video_pagestart, GET_FARVAR(ES, *(u16*)(BX+0)));
1888 SET_BDA(video_page, GET_FARVAR(ES, *(u8*)(BX+0)));
1891 SET_IVT(0x1f, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
1893 SET_IVT(0x43, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
1898 u16 v = GET_FARVAR(ES, *(u8*)(BX+0));
1900 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_PEL_MASK);
1902 // Set the whole dac always, from 0
1903 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
1905 for (i = 0; i < 256 * 3; i++) {
1906 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_DAC_DATA);
1910 outb(v, VGAREG_DAC_WRITE_ADDRESS);
1916 /****************************************************************
1917 * VGA int 10 handler
1918 ****************************************************************/
1921 handle_1000(struct bregs *regs)
1924 biosfn_set_video_mode(regs->al);
1925 switch(regs->al & 0x7F) {
1944 handle_1001(struct bregs *regs)
1946 biosfn_set_cursor_shape(regs->ch, regs->cl);
1950 handle_1002(struct bregs *regs)
1952 biosfn_set_cursor_pos(regs->bh, regs->dx);
1956 handle_1003(struct bregs *regs)
1958 regs->cx = biosfn_get_cursor_shape(regs->bh);
1959 regs->dx = biosfn_get_cursor_pos(regs->bh);
1962 // Read light pen pos (unimplemented)
1964 handle_1004(struct bregs *regs)
1967 regs->ax = regs->bx = regs->cx = regs->dx = 0;
1971 handle_1005(struct bregs *regs)
1973 biosfn_set_active_page(regs->al);
1977 handle_1006(struct bregs *regs)
1979 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
1984 handle_1007(struct bregs *regs)
1986 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
1987 , 0xFF, SCROLL_DOWN);
1991 handle_1008(struct bregs *regs)
1994 biosfn_read_char_attr(regs->bh, ®s->ax);
1998 handle_1009(struct bregs *regs)
2001 biosfn_write_char_attr(regs->al, regs->bh, regs->bl, regs->cx);
2005 handle_100a(struct bregs *regs)
2008 biosfn_write_char_only(regs->al, regs->bh, regs->bl, regs->cx);
2013 handle_100b00(struct bregs *regs)
2016 biosfn_set_border_color(regs);
2020 handle_100b01(struct bregs *regs)
2023 biosfn_set_palette(regs);
2027 handle_100bXX(struct bregs *regs)
2033 handle_100b(struct bregs *regs)
2036 case 0x00: handle_100b00(regs); break;
2037 case 0x01: handle_100b01(regs); break;
2038 default: handle_100bXX(regs); break;
2044 handle_100c(struct bregs *regs)
2047 biosfn_write_pixel(regs->bh, regs->al, regs->cx, regs->dx);
2051 handle_100d(struct bregs *regs)
2054 biosfn_read_pixel(regs->bh, regs->cx, regs->dx, ®s->ax);
2058 handle_100e(struct bregs *regs)
2060 // Ralf Brown Interrupt list is WRONG on bh(page)
2061 // We do output only on the current page !
2062 biosfn_write_teletype(regs->al, 0xff, regs->bl, NO_ATTR);
2066 handle_100f(struct bregs *regs)
2069 biosfn_get_video_mode(regs);
2074 handle_101000(struct bregs *regs)
2076 if (regs->bl > 0x14)
2078 biosfn_set_single_palette_reg(regs->bl, regs->bh);
2082 handle_101001(struct bregs *regs)
2085 biosfn_set_overscan_border_color(regs);
2089 handle_101002(struct bregs *regs)
2092 biosfn_set_all_palette_reg(regs);
2096 handle_101003(struct bregs *regs)
2099 biosfn_toggle_intensity(regs);
2103 handle_101007(struct bregs *regs)
2105 if (regs->bl > 0x14)
2107 regs->bh = biosfn_get_single_palette_reg(regs->bl);
2111 handle_101008(struct bregs *regs)
2114 biosfn_read_overscan_border_color(regs);
2118 handle_101009(struct bregs *regs)
2121 biosfn_get_all_palette_reg(regs);
2125 handle_101010(struct bregs *regs)
2128 biosfn_set_single_dac_reg(regs);
2132 handle_101012(struct bregs *regs)
2135 biosfn_set_all_dac_reg(regs);
2139 handle_101013(struct bregs *regs)
2142 biosfn_select_video_dac_color_page(regs);
2146 handle_101015(struct bregs *regs)
2149 biosfn_read_single_dac_reg(regs);
2153 handle_101017(struct bregs *regs)
2156 biosfn_read_all_dac_reg(regs);
2160 handle_101018(struct bregs *regs)
2163 biosfn_set_pel_mask(regs);
2167 handle_101019(struct bregs *regs)
2170 biosfn_read_pel_mask(regs);
2174 handle_10101a(struct bregs *regs)
2177 biosfn_read_video_dac_state(regs);
2181 handle_10101b(struct bregs *regs)
2183 biosfn_perform_gray_scale_summing(regs->bx, regs->cx);
2187 handle_1010XX(struct bregs *regs)
2193 handle_1010(struct bregs *regs)
2196 case 0x00: handle_101000(regs); break;
2197 case 0x01: handle_101001(regs); break;
2198 case 0x02: handle_101002(regs); break;
2199 case 0x03: handle_101003(regs); break;
2200 case 0x07: handle_101007(regs); break;
2201 case 0x08: handle_101008(regs); break;
2202 case 0x09: handle_101009(regs); break;
2203 case 0x10: handle_101010(regs); break;
2204 case 0x12: handle_101012(regs); break;
2205 case 0x13: handle_101013(regs); break;
2206 case 0x15: handle_101015(regs); break;
2207 case 0x17: handle_101017(regs); break;
2208 case 0x18: handle_101018(regs); break;
2209 case 0x19: handle_101019(regs); break;
2210 case 0x1a: handle_10101a(regs); break;
2211 case 0x1b: handle_10101b(regs); break;
2212 default: handle_1010XX(regs); break;
2218 handle_101100(struct bregs *regs)
2221 biosfn_load_text_user_pat(regs->al, regs->es, 0 // XXX - regs->bp
2222 , regs->cx, regs->dx, regs->bl, regs->bh);
2226 handle_101101(struct bregs *regs)
2229 biosfn_load_text_8_14_pat(regs->al, regs->bl);
2233 handle_101102(struct bregs *regs)
2236 biosfn_load_text_8_8_pat(regs->al, regs->bl);
2240 handle_101103(struct bregs *regs)
2243 biosfn_set_text_block_specifier(regs);
2247 handle_101104(struct bregs *regs)
2250 biosfn_load_text_8_16_pat(regs->al, regs->bl);
2254 handle_101110(struct bregs *regs)
2256 handle_101100(regs);
2260 handle_101111(struct bregs *regs)
2262 handle_101101(regs);
2266 handle_101112(struct bregs *regs)
2268 handle_101102(regs);
2272 handle_101114(struct bregs *regs)
2274 handle_101104(regs);
2278 handle_101130(struct bregs *regs)
2281 biosfn_get_font_info(regs->bh, ®s->es, 0 // ®s->bp
2282 , ®s->cx, ®s->dx);
2286 handle_1011XX(struct bregs *regs)
2292 handle_1011(struct bregs *regs)
2295 case 0x00: handle_101100(regs); break;
2296 case 0x01: handle_101101(regs); break;
2297 case 0x02: handle_101102(regs); break;
2298 case 0x03: handle_101103(regs); break;
2299 case 0x04: handle_101104(regs); break;
2300 case 0x10: handle_101110(regs); break;
2301 case 0x11: handle_101111(regs); break;
2302 case 0x12: handle_101112(regs); break;
2303 case 0x14: handle_101114(regs); break;
2304 case 0x30: handle_101130(regs); break;
2305 default: handle_1011XX(regs); break;
2311 handle_101210(struct bregs *regs)
2314 biosfn_get_ega_info(regs);
2318 handle_101230(struct bregs *regs)
2321 biosfn_select_vert_res(regs);
2325 handle_101231(struct bregs *regs)
2328 biosfn_enable_default_palette_loading(regs);
2332 handle_101232(struct bregs *regs)
2335 biosfn_enable_video_addressing(regs);
2339 handle_101233(struct bregs *regs)
2342 biosfn_enable_grayscale_summing(regs);
2346 handle_101234(struct bregs *regs)
2349 biosfn_enable_cursor_emulation(regs);
2353 handle_101235(struct bregs *regs)
2360 handle_101236(struct bregs *regs)
2367 handle_1012XX(struct bregs *regs)
2373 handle_1012(struct bregs *regs)
2376 case 0x10: handle_101210(regs); break;
2377 case 0x30: handle_101230(regs); break;
2378 case 0x31: handle_101231(regs); break;
2379 case 0x32: handle_101232(regs); break;
2380 case 0x33: handle_101233(regs); break;
2381 case 0x34: handle_101234(regs); break;
2382 case 0x35: handle_101235(regs); break;
2383 case 0x36: handle_101236(regs); break;
2384 default: handle_1012XX(regs); break;
2387 // XXX - cirrus has 1280, 1281, 1282, 1285, 129a, 12a0, 12a1, 12a2, 12ae
2392 handle_1013(struct bregs *regs)
2395 biosfn_write_string(regs->al, regs->bh, regs->bl, regs->cx
2396 , regs->dh, regs->dl, regs->es, 0); // regs->bp);
2401 handle_101a00(struct bregs *regs)
2404 biosfn_read_display_code(regs);
2408 handle_101a01(struct bregs *regs)
2411 biosfn_set_display_code(regs);
2415 handle_101aXX(struct bregs *regs)
2421 handle_101a(struct bregs *regs)
2424 case 0x00: handle_101a00(regs); break;
2425 case 0x01: handle_101a01(regs); break;
2426 default: handle_101aXX(regs); break;
2432 handle_101b(struct bregs *regs)
2435 biosfn_read_state_info(regs->bx, regs->es, regs->di);
2441 handle_101c00(struct bregs *regs)
2444 regs->bx = biosfn_read_video_state_size(regs->cx);
2448 handle_101c01(struct bregs *regs)
2451 biosfn_save_video_state(regs->cx, regs->es, regs->bx);
2455 handle_101c02(struct bregs *regs)
2458 biosfn_restore_video_state(regs->cx, regs->es, regs->bx);
2462 handle_101cXX(struct bregs *regs)
2468 handle_101c(struct bregs *regs)
2471 case 0x00: handle_101c00(regs); break;
2472 case 0x01: handle_101c01(regs); break;
2473 case 0x02: handle_101c02(regs); break;
2474 default: handle_101cXX(regs); break;
2480 handle_104f00(struct bregs *regs)
2482 // XXX - vbe_biosfn_return_controller_information(&AX,ES,DI);
2483 // XXX - OR cirrus_vesa_00h
2487 handle_104f01(struct bregs *regs)
2489 // XXX - vbe_biosfn_return_mode_information(&AX,CX,ES,DI);
2490 // XXX - OR cirrus_vesa_01h
2494 handle_104f02(struct bregs *regs)
2496 // XXX - vbe_biosfn_set_mode(&AX,BX,ES,DI);
2497 // XXX - OR cirrus_vesa_02h
2501 handle_104f03(struct bregs *regs)
2503 // XXX - vbe_biosfn_return_current_mode
2504 // XXX - OR cirrus_vesa_03h
2508 handle_104f04(struct bregs *regs)
2510 // XXX - vbe_biosfn_save_restore_state(&AX, CX, DX, ES, &BX);
2514 handle_104f05(struct bregs *regs)
2516 // XXX - vbe_biosfn_display_window_control
2517 // XXX - OR cirrus_vesa_05h
2521 handle_104f06(struct bregs *regs)
2523 // XXX - vbe_biosfn_set_get_logical_scan_line_length
2524 // XXX - OR cirrus_vesa_06h
2528 handle_104f07(struct bregs *regs)
2530 // XXX - vbe_biosfn_set_get_display_start
2531 // XXX - OR cirrus_vesa_07h
2535 handle_104f08(struct bregs *regs)
2537 // XXX - vbe_biosfn_set_get_dac_palette_format
2541 handle_104f0a(struct bregs *regs)
2543 // XXX - vbe_biosfn_return_protected_mode_interface
2547 handle_104fXX(struct bregs *regs)
2554 handle_104f(struct bregs *regs)
2557 handle_104fXX(regs);
2561 // XXX - check vbe_has_vbe_display()?
2564 case 0x00: handle_104f00(regs); break;
2565 case 0x01: handle_104f01(regs); break;
2566 case 0x02: handle_104f02(regs); break;
2567 case 0x03: handle_104f03(regs); break;
2568 case 0x04: handle_104f04(regs); break;
2569 case 0x05: handle_104f05(regs); break;
2570 case 0x06: handle_104f06(regs); break;
2571 case 0x07: handle_104f07(regs); break;
2572 case 0x08: handle_104f08(regs); break;
2573 case 0x0a: handle_104f0a(regs); break;
2574 default: handle_104fXX(regs); break;
2580 handle_10XX(struct bregs *regs)
2585 // INT 10h Video Support Service Entry Point
2587 handle_10(struct bregs *regs)
2589 debug_enter(regs, DEBUG_VGA_10);
2591 case 0x00: handle_1000(regs); break;
2592 case 0x01: handle_1001(regs); break;
2593 case 0x02: handle_1002(regs); break;
2594 case 0x03: handle_1003(regs); break;
2595 case 0x04: handle_1004(regs); break;
2596 case 0x05: handle_1005(regs); break;
2597 case 0x06: handle_1006(regs); break;
2598 case 0x07: handle_1007(regs); break;
2599 case 0x08: handle_1008(regs); break;
2600 case 0x09: handle_1009(regs); break;
2601 case 0x0a: handle_100a(regs); break;
2602 case 0x0b: handle_100b(regs); break;
2603 case 0x0c: handle_100c(regs); break;
2604 case 0x0d: handle_100d(regs); break;
2605 case 0x0e: handle_100e(regs); break;
2606 case 0x0f: handle_100f(regs); break;
2607 case 0x10: handle_1010(regs); break;
2608 case 0x11: handle_1011(regs); break;
2609 case 0x12: handle_1012(regs); break;
2610 case 0x13: handle_1013(regs); break;
2611 case 0x1a: handle_101a(regs); break;
2612 case 0x1b: handle_101b(regs); break;
2613 case 0x1c: handle_101c(regs); break;
2614 case 0x4f: handle_104f(regs); break;
2615 default: handle_10XX(regs); break;
2620 /****************************************************************
2622 ****************************************************************/
2627 // init detected hardware BIOS Area
2628 // set 80x25 color (not clear from RBIL but usual)
2629 u16 eqf = GET_BDA(equipment_list_flags);
2630 SET_BDA(equipment_list_flags, (eqf & 0xffcf) | 0x20);
2632 // Just for the first int10 find its children
2634 // the default char height
2635 SET_BDA(char_height, 0x10);
2638 SET_BDA(video_ctl, 0x60);
2640 // Set the basic screen we have
2641 SET_BDA(video_switches, 0xf9);
2643 // Set the basic modeset options
2644 SET_BDA(modeset_ctl, 0x51);
2646 // Set the default MSR
2647 SET_BDA(video_msr, 0x09);
2653 // switch to color mode and enable CPU access 480 lines
2654 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
2655 // more than 64k 3C4/04
2656 outb(0x04, VGAREG_SEQU_ADDRESS);
2657 outb(0x02, VGAREG_SEQU_DATA);
2661 vga_post(struct bregs *regs)
2663 debug_enter(regs, DEBUG_VGA_POST);
2672 extern void entry_10(void);
2673 SET_IVT(0x10, get_global_seg(), (u32)entry_10);
2678 // XXX - clear screen and display info
2681 SET_VGA(video_save_pointer_table[0], (u32)video_param_table);
2682 SET_VGA(video_save_pointer_table[1], get_global_seg());
2685 extern u8 _rom_header_size, _rom_header_checksum;
2686 SET_VGA(_rom_header_checksum, 0);
2687 u8 sum = -checksum_far(get_global_seg(), 0, _rom_header_size * 512);
2688 SET_VGA(_rom_header_checksum, sum);