1 // VGA bios implementation
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
10 // * review correctness of converted asm by comparing with RBIL
11 // * refactor redundant code into sub-functions
12 // * See if there is a method to the in/out stuff that can be encapsulated.
13 // * remove "biosfn" prefixes
14 // * verify all funcs static
16 // * convert vbe/clext code
18 // * extract hw code from bios interfaces
20 #include "bregs.h" // struct bregs
21 #include "biosvar.h" // GET_BDA
22 #include "util.h" // memset
23 #include "vgatables.h" // find_vga_entry
27 #define CONFIG_CIRRUS 0
30 #define DEBUG_VGA_POST 1
31 #define DEBUG_VGA_10 3
33 #define SET_VGA(var, val) SET_FARVAR(get_global_seg(), (var), (val))
36 // ===================================================================
40 // ===================================================================
42 // -------------------------------------------------------------------
44 call16_vgaint(u32 eax, u32 ebx)
56 // ===================================================================
60 // ===================================================================
62 // -------------------------------------------------------------------
64 biosfn_perform_gray_scale_summing(u16 start, u16 count)
66 vgahw_screen_disable();
68 for (i = start; i < start+count; i++) {
70 vgahw_get_dac_regs(GET_SEG(SS), rgb, i, 1);
72 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
73 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
77 vgahw_set_dac_regs(GET_SEG(SS), rgb, i, 1);
79 vgahw_screen_enable();
82 // -------------------------------------------------------------------
84 biosfn_set_cursor_shape(u8 CH, u8 CL)
89 u16 curs = (CH << 8) + CL;
90 SET_BDA(cursor_type, curs);
92 u8 modeset_ctl = GET_BDA(modeset_ctl);
93 u16 cheight = GET_BDA(char_height);
94 if ((modeset_ctl & 0x01) && (cheight > 8) && (CL < 8) && (CH < 0x20)) {
96 CH = ((CH + 1) * cheight / 8) - 1;
98 CH = ((CL + 1) * cheight / 8) - 2;
99 CL = ((CL + 1) * cheight / 8) - 1;
101 vgahw_set_cursor_shape(CH, CL);
105 biosfn_get_cursor_shape(u8 page)
109 // FIXME should handle VGA 14/16 lines
110 return GET_BDA(cursor_type);
113 // -------------------------------------------------------------------
115 biosfn_set_cursor_pos(u8 page, u16 cursor)
117 // Should not happen...
122 SET_BDA(cursor_pos[page], cursor);
124 // Set the hardware cursor
125 u8 current = GET_BDA(video_page);
129 // Get the dimensions
130 u16 nbcols = GET_BDA(video_cols);
131 u16 nbrows = GET_BDA(video_rows) + 1;
133 u8 xcurs = cursor & 0x00ff;
134 u8 ycurs = (cursor & 0xff00) >> 8;
136 // Calculate the address knowing nbcols nbrows and page num
137 u16 address = SCREEN_IO_START(nbcols, nbrows, page) + xcurs + ycurs * nbcols;
139 vgahw_set_cursor_pos(address);
143 biosfn_get_cursor_pos(u8 page)
147 // FIXME should handle VGA 14/16 lines
148 return GET_BDA(cursor_pos[page]);
151 // -------------------------------------------------------------------
153 biosfn_set_active_page(u8 page)
159 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
163 // Get pos curs pos for the right page
164 u16 cursor = biosfn_get_cursor_pos(page);
167 if (GET_GLOBAL(vmode_g->class) == TEXT) {
168 // Get the dimensions
169 u16 nbcols = GET_BDA(video_cols);
170 u16 nbrows = GET_BDA(video_rows) + 1;
172 // Calculate the address knowing nbcols nbrows and page num
173 address = SCREEN_MEM_START(nbcols, nbrows, page);
174 SET_BDA(video_pagestart, address);
177 address = SCREEN_IO_START(nbcols, nbrows, page);
179 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
180 address = page * GET_GLOBAL(vparam_g->slength);
183 vgahw_set_active_page(address);
185 // And change the BIOS page
186 SET_BDA(video_page, page);
188 dprintf(1, "Set active page %02x address %04x\n", page, address);
190 // Display the cursor, now the page is active
191 biosfn_set_cursor_pos(page, cursor);
195 biosfn_set_video_mode(u8 mode)
196 { // mode: Bit 7 is 1 if no clear screen
198 cirrus_set_video_mode(mode);
201 if (vbe_has_vbe_display())
202 dispi_set_enable(VBE_DISPI_DISABLED);
205 u8 noclearmem = mode & 0x80;
208 // find the entry in the video modes
209 struct vgamode_s *vmode_g = find_vga_entry(mode);
210 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
214 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
215 u16 twidth = GET_GLOBAL(vparam_g->twidth);
216 u16 theightm1 = GET_GLOBAL(vparam_g->theightm1);
217 u16 cheight = GET_GLOBAL(vparam_g->cheight);
219 // Read the bios mode set control
220 u8 modeset_ctl = GET_BDA(modeset_ctl);
222 // Then we know the number of lines
225 // if palette loading (bit 3 of modeset ctl = 0)
226 if ((modeset_ctl & 0x08) == 0) { // Set the PEL mask
227 outb(GET_GLOBAL(vmode_g->pelmask), VGAREG_PEL_MASK);
229 // Set the whole dac always, from 0
230 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
232 // From which palette
233 u8 *palette_g = GET_GLOBAL(vmode_g->dac);
234 u16 palsize = GET_GLOBAL(vmode_g->dacsize) / 3;
235 // Always 256*3 values
237 for (i = 0; i < 0x0100; i++) {
239 outb(GET_GLOBAL(palette_g[(i * 3) + 0]), VGAREG_DAC_DATA);
240 outb(GET_GLOBAL(palette_g[(i * 3) + 1]), VGAREG_DAC_DATA);
241 outb(GET_GLOBAL(palette_g[(i * 3) + 2]), VGAREG_DAC_DATA);
243 outb(0, VGAREG_DAC_DATA);
244 outb(0, VGAREG_DAC_DATA);
245 outb(0, VGAREG_DAC_DATA);
248 if ((modeset_ctl & 0x02) == 0x02)
249 biosfn_perform_gray_scale_summing(0x00, 0x100);
251 // Reset Attribute Ctl flip-flop
252 inb(VGAREG_ACTL_RESET);
256 for (i = 0; i <= 0x13; i++) {
257 outb(i, VGAREG_ACTL_ADDRESS);
258 outb(GET_GLOBAL(vparam_g->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
260 outb(0x14, VGAREG_ACTL_ADDRESS);
261 outb(0x00, VGAREG_ACTL_WRITE_DATA);
264 outb(0, VGAREG_SEQU_ADDRESS);
265 outb(0x03, VGAREG_SEQU_DATA);
266 for (i = 1; i <= 4; i++) {
267 outb(i, VGAREG_SEQU_ADDRESS);
268 outb(GET_GLOBAL(vparam_g->sequ_regs[i - 1]), VGAREG_SEQU_DATA);
272 for (i = 0; i <= 8; i++) {
273 outb(i, VGAREG_GRDC_ADDRESS);
274 outb(GET_GLOBAL(vparam_g->grdc_regs[i]), VGAREG_GRDC_DATA);
277 // Set CRTC address VGA or MDA
278 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
279 if (GET_GLOBAL(vmode_g->memmodel) == MTEXT)
280 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
282 // Disable CRTC write protection
283 outw(0x0011, crtc_addr);
285 for (i = 0; i <= 0x18; i++) {
287 outb(GET_GLOBAL(vparam_g->crtc_regs[i]), crtc_addr + 1);
290 // Set the misc register
291 outb(GET_GLOBAL(vparam_g->miscreg), VGAREG_WRITE_MISC_OUTPUT);
294 outb(0x20, VGAREG_ACTL_ADDRESS);
295 inb(VGAREG_ACTL_RESET);
297 if (noclearmem == 0x00) {
298 if (GET_GLOBAL(vmode_g->class) == TEXT) {
299 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
302 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
304 outb(0x02, VGAREG_SEQU_ADDRESS);
305 u8 mmask = inb(VGAREG_SEQU_DATA);
306 outb(0x0f, VGAREG_SEQU_DATA); // all planes
307 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
308 outb(mmask, VGAREG_SEQU_DATA);
313 SET_BDA(video_mode, mode);
314 SET_BDA(video_cols, twidth);
315 SET_BDA(video_pagesize, GET_GLOBAL(vparam_g->slength));
316 SET_BDA(crtc_address, crtc_addr);
317 SET_BDA(video_rows, theightm1);
318 SET_BDA(char_height, cheight);
319 SET_BDA(video_ctl, (0x60 | noclearmem));
320 SET_BDA(video_switches, 0xF9);
321 SET_BDA(modeset_ctl, GET_BDA(modeset_ctl) & 0x7f);
323 // FIXME We nearly have the good tables. to be reworked
324 SET_BDA(dcc_index, 0x08); // 8 is VGA should be ok for now
325 SET_BDA(video_savetable_ptr, (u32)video_save_pointer_table);
326 SET_BDA(video_savetable_seg, get_global_seg());
329 SET_BDA(video_msr, 0x00); // Unavailable on vanilla vga, but...
330 SET_BDA(video_pal, 0x00); // Unavailable on vanilla vga, but...
333 if (GET_GLOBAL(vmode_g->class) == TEXT)
334 biosfn_set_cursor_shape(0x06, 0x07);
335 // Set cursor pos for page 0..7
336 for (i = 0; i < 8; i++)
337 biosfn_set_cursor_pos(i, 0x0000);
340 biosfn_set_active_page(0x00);
342 // Write the fonts in memory
343 if (GET_GLOBAL(vmode_g->class) == TEXT) {
344 call16_vgaint(0x1104, 0);
345 call16_vgaint(0x1103, 0);
347 // Set the ints 0x1F and 0x43
348 SET_IVT(0x1f, get_global_seg(), (u32)&vgafont8[128 * 8]);
352 SET_IVT(0x43, get_global_seg(), (u32)vgafont8);
355 SET_IVT(0x43, get_global_seg(), (u32)vgafont14);
358 SET_IVT(0x43, get_global_seg(), (u32)vgafont16);
363 // -------------------------------------------------------------------
365 biosfn_write_teletype(u8 car, u8 page, u8 attr, u8 flag)
366 { // flag = WITH_ATTR / NO_ATTR
367 // special case if page is 0xff, use current page
369 page = GET_BDA(video_page);
372 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
376 // Get the cursor pos for the page
377 u16 cursor = biosfn_get_cursor_pos(page);
378 u8 xcurs = cursor & 0x00ff;
379 u8 ycurs = (cursor & 0xff00) >> 8;
381 // Get the dimensions
382 u16 nbrows = GET_BDA(video_rows) + 1;
383 u16 nbcols = GET_BDA(video_cols);
405 biosfn_write_teletype(' ', page, attr, flag);
406 cursor = biosfn_get_cursor_pos(page);
407 xcurs = cursor & 0x00ff;
408 ycurs = (cursor & 0xff00) >> 8;
409 } while (xcurs % 8 == 0);
413 if (flag == WITH_ATTR)
414 biosfn_write_char_attr(car, page, attr, 1);
416 biosfn_write_char_only(car, page, attr, 1);
420 // Do we need to wrap ?
421 if (xcurs == nbcols) {
425 // Do we need to scroll ?
426 if (ycurs == nbrows) {
427 if (GET_GLOBAL(vmode_g->class) == TEXT)
428 biosfn_scroll(0x01, 0x07, 0, 0, nbrows - 1, nbcols - 1, page,
431 biosfn_scroll(0x01, 0x00, 0, 0, nbrows - 1, nbcols - 1, page,
435 // Set the cursor for the page
439 biosfn_set_cursor_pos(page, cursor);
443 biosfn_write_string(u8 flag, u8 page, u8 attr, u16 count, u8 row, u8 col,
444 u16 seg, u8 *offset_far)
446 // Read curs info for the page
447 u16 oldcurs = biosfn_get_cursor_pos(page);
449 // if row=0xff special case : use current cursor position
451 col = oldcurs & 0x00ff;
452 row = (oldcurs & 0xff00) >> 8;
458 biosfn_set_cursor_pos(page, newcurs);
460 while (count-- != 0) {
461 u8 car = GET_FARVAR(seg, *offset_far);
463 if ((flag & 0x02) != 0) {
464 attr = GET_FARVAR(seg, *offset_far);
468 biosfn_write_teletype(car, page, attr, WITH_ATTR);
472 if ((flag & 0x01) == 0)
473 biosfn_set_cursor_pos(page, oldcurs);
477 set_scan_lines(u8 lines)
479 vgahw_set_scan_lines(lines);
481 biosfn_set_cursor_shape(0x06, 0x07);
483 biosfn_set_cursor_shape(lines - 4, lines - 3);
484 SET_BDA(char_height, lines);
485 u16 vde = vgahw_get_vde();
486 u8 rows = vde / lines;
487 SET_BDA(video_rows, rows - 1);
488 u16 cols = GET_BDA(video_cols);
489 SET_BDA(video_pagesize, rows * cols * 2);
493 biosfn_save_bda_state(u16 seg, struct saveBDAstate *info)
495 SET_FARVAR(seg, info->video_mode, GET_BDA(video_mode));
496 SET_FARVAR(seg, info->video_cols, GET_BDA(video_cols));
497 SET_FARVAR(seg, info->video_pagesize, GET_BDA(video_pagesize));
498 SET_FARVAR(seg, info->crtc_address, GET_BDA(crtc_address));
499 SET_FARVAR(seg, info->video_rows, GET_BDA(video_rows));
500 SET_FARVAR(seg, info->char_height, GET_BDA(char_height));
501 SET_FARVAR(seg, info->video_ctl, GET_BDA(video_ctl));
502 SET_FARVAR(seg, info->video_switches, GET_BDA(video_switches));
503 SET_FARVAR(seg, info->modeset_ctl, GET_BDA(modeset_ctl));
504 SET_FARVAR(seg, info->cursor_type, GET_BDA(cursor_type));
507 SET_FARVAR(seg, info->cursor_pos[i], GET_BDA(cursor_pos[i]));
508 SET_FARVAR(seg, info->video_pagestart, GET_BDA(video_pagestart));
509 SET_FARVAR(seg, info->video_page, GET_BDA(video_page));
511 SET_FARVAR(seg, *(u32*)&info->font0_off, GET_IVT(0x1f).segoff);
512 SET_FARVAR(seg, *(u32*)&info->font1_off, GET_IVT(0x43).segoff);
516 biosfn_restore_bda_state(u16 seg, struct saveBDAstate *info)
518 SET_BDA(video_mode, GET_FARVAR(seg, info->video_mode));
519 SET_BDA(video_cols, GET_FARVAR(seg, info->video_cols));
520 SET_BDA(video_pagesize, GET_FARVAR(seg, info->video_pagesize));
521 SET_BDA(crtc_address, GET_FARVAR(seg, info->crtc_address));
522 SET_BDA(video_rows, GET_FARVAR(seg, info->video_rows));
523 SET_BDA(char_height, GET_FARVAR(seg, info->char_height));
524 SET_BDA(video_ctl, GET_FARVAR(seg, info->video_ctl));
525 SET_BDA(video_switches, GET_FARVAR(seg, info->video_switches));
526 SET_BDA(modeset_ctl, GET_FARVAR(seg, info->modeset_ctl));
527 SET_BDA(cursor_type, GET_FARVAR(seg, info->cursor_type));
529 for (i = 0; i < 8; i++)
530 SET_BDA(cursor_pos[i], GET_FARVAR(seg, info->cursor_pos[i]));
531 SET_BDA(video_pagestart, GET_FARVAR(seg, info->video_pagestart));
532 SET_BDA(video_page, GET_FARVAR(seg, info->video_page));
534 SET_IVT(0x1f, GET_FARVAR(seg, info->font0_seg)
535 , GET_FARVAR(seg, info->font0_off));
536 SET_IVT(0x43, GET_FARVAR(seg, info->font1_seg)
537 , GET_FARVAR(seg, info->font1_off));
541 /****************************************************************
543 ****************************************************************/
546 handle_1000(struct bregs *regs)
549 biosfn_set_video_mode(regs->al);
550 switch(regs->al & 0x7F) {
569 handle_1001(struct bregs *regs)
571 biosfn_set_cursor_shape(regs->ch, regs->cl);
575 handle_1002(struct bregs *regs)
577 biosfn_set_cursor_pos(regs->bh, regs->dx);
581 handle_1003(struct bregs *regs)
583 regs->cx = biosfn_get_cursor_shape(regs->bh);
584 regs->dx = biosfn_get_cursor_pos(regs->bh);
587 // Read light pen pos (unimplemented)
589 handle_1004(struct bregs *regs)
592 regs->ax = regs->bx = regs->cx = regs->dx = 0;
596 handle_1005(struct bregs *regs)
598 biosfn_set_active_page(regs->al);
602 handle_1006(struct bregs *regs)
604 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
609 handle_1007(struct bregs *regs)
611 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
612 , 0xFF, SCROLL_DOWN);
616 handle_1008(struct bregs *regs)
619 biosfn_read_char_attr(regs->bh, ®s->ax);
623 handle_1009(struct bregs *regs)
626 biosfn_write_char_attr(regs->al, regs->bh, regs->bl, regs->cx);
630 handle_100a(struct bregs *regs)
633 biosfn_write_char_only(regs->al, regs->bh, regs->bl, regs->cx);
638 handle_100b00(struct bregs *regs)
640 vgahw_set_border_color(regs->bl);
644 handle_100b01(struct bregs *regs)
646 vgahw_set_palette(regs->bl);
650 handle_100bXX(struct bregs *regs)
656 handle_100b(struct bregs *regs)
659 case 0x00: handle_100b00(regs); break;
660 case 0x01: handle_100b01(regs); break;
661 default: handle_100bXX(regs); break;
667 handle_100c(struct bregs *regs)
670 biosfn_write_pixel(regs->bh, regs->al, regs->cx, regs->dx);
674 handle_100d(struct bregs *regs)
677 biosfn_read_pixel(regs->bh, regs->cx, regs->dx, ®s->ax);
681 handle_100e(struct bregs *regs)
683 // Ralf Brown Interrupt list is WRONG on bh(page)
684 // We do output only on the current page !
685 biosfn_write_teletype(regs->al, 0xff, regs->bl, NO_ATTR);
689 handle_100f(struct bregs *regs)
691 regs->bh = GET_BDA(video_page);
692 regs->al = GET_BDA(video_mode) | (GET_BDA(video_ctl) & 0x80);
693 regs->ah = GET_BDA(video_cols);
698 handle_101000(struct bregs *regs)
702 vgahw_set_single_palette_reg(regs->bl, regs->bh);
706 handle_101001(struct bregs *regs)
708 vgahw_set_overscan_border_color(regs->bh);
712 handle_101002(struct bregs *regs)
714 vgahw_set_all_palette_reg(regs->es, (u8*)(regs->dx + 0));
718 handle_101003(struct bregs *regs)
720 vgahw_toggle_intensity(regs->bl);
724 handle_101007(struct bregs *regs)
728 regs->bh = vgahw_get_single_palette_reg(regs->bl);
732 handle_101008(struct bregs *regs)
734 regs->bh = vgahw_get_overscan_border_color(regs);
738 handle_101009(struct bregs *regs)
740 vgahw_get_all_palette_reg(regs->es, (u8*)(regs->dx + 0));
744 handle_101010(struct bregs *regs)
746 u8 rgb[3] = {regs->dh, regs->ch, regs->cl};
747 vgahw_set_dac_regs(GET_SEG(SS), rgb, regs->bx, 1);
751 handle_101012(struct bregs *regs)
753 vgahw_set_dac_regs(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx);
757 handle_101013(struct bregs *regs)
759 vgahw_select_video_dac_color_page(regs->bl, regs->bh);
763 handle_101015(struct bregs *regs)
766 vgahw_get_dac_regs(GET_SEG(SS), rgb, regs->bx, 1);
773 handle_101017(struct bregs *regs)
775 vgahw_get_dac_regs(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx);
779 handle_101018(struct bregs *regs)
781 vgahw_set_pel_mask(regs->bl);
785 handle_101019(struct bregs *regs)
787 regs->bl = vgahw_get_pel_mask();
791 handle_10101a(struct bregs *regs)
793 vgahw_read_video_dac_state(®s->bl, ®s->bh);
797 handle_10101b(struct bregs *regs)
799 biosfn_perform_gray_scale_summing(regs->bx, regs->cx);
803 handle_1010XX(struct bregs *regs)
809 handle_1010(struct bregs *regs)
812 case 0x00: handle_101000(regs); break;
813 case 0x01: handle_101001(regs); break;
814 case 0x02: handle_101002(regs); break;
815 case 0x03: handle_101003(regs); break;
816 case 0x07: handle_101007(regs); break;
817 case 0x08: handle_101008(regs); break;
818 case 0x09: handle_101009(regs); break;
819 case 0x10: handle_101010(regs); break;
820 case 0x12: handle_101012(regs); break;
821 case 0x13: handle_101013(regs); break;
822 case 0x15: handle_101015(regs); break;
823 case 0x17: handle_101017(regs); break;
824 case 0x18: handle_101018(regs); break;
825 case 0x19: handle_101019(regs); break;
826 case 0x1a: handle_10101a(regs); break;
827 case 0x1b: handle_10101b(regs); break;
828 default: handle_1010XX(regs); break;
834 handle_101100(struct bregs *regs)
836 biosfn_load_text_user_pat(regs->es, regs->bp
837 , regs->cx, regs->dx, regs->bl, regs->bh);
841 handle_101101(struct bregs *regs)
843 biosfn_load_text_8_14_pat(regs->bl);
847 handle_101102(struct bregs *regs)
849 biosfn_load_text_8_8_pat(regs->bl);
853 handle_101103(struct bregs *regs)
855 vgahw_set_text_block_specifier(regs->bl);
859 handle_101104(struct bregs *regs)
861 biosfn_load_text_8_16_pat(regs->bl);
865 handle_101110(struct bregs *regs)
867 biosfn_load_text_user_pat(regs->es, regs->bp
868 , regs->cx, regs->dx, regs->bl, regs->bh);
869 set_scan_lines(regs->bh);
873 handle_101111(struct bregs *regs)
875 biosfn_load_text_8_14_pat(regs->bl);
880 handle_101112(struct bregs *regs)
882 biosfn_load_text_8_8_pat(regs->bl);
887 handle_101114(struct bregs *regs)
889 biosfn_load_text_8_16_pat(regs->bl);
894 handle_101130(struct bregs *regs)
898 u32 segoff = GET_IVT(0x1f).segoff;
899 regs->es = segoff >> 16;
904 u32 segoff = GET_IVT(0x43).segoff;
905 regs->es = segoff >> 16;
910 regs->es = get_global_seg();
911 regs->bp = (u32)vgafont14;
914 regs->es = get_global_seg();
915 regs->bp = (u32)vgafont8;
918 regs->es = get_global_seg();
919 regs->bp = (u32)vgafont8 + 128 * 8;
922 regs->es = get_global_seg();
923 regs->bp = (u32)vgafont14alt;
926 regs->es = get_global_seg();
927 regs->bp = (u32)vgafont16;
930 regs->es = get_global_seg();
931 regs->bp = (u32)vgafont16alt;
934 dprintf(1, "Get font info BH(%02x) was discarded\n", regs->bh);
937 // Set byte/char of on screen font
938 regs->cx = GET_BDA(char_height) & 0xff;
940 // Set Highest char row
941 regs->dx = GET_BDA(video_rows);
945 handle_1011XX(struct bregs *regs)
951 handle_1011(struct bregs *regs)
954 case 0x00: handle_101100(regs); break;
955 case 0x01: handle_101101(regs); break;
956 case 0x02: handle_101102(regs); break;
957 case 0x03: handle_101103(regs); break;
958 case 0x04: handle_101104(regs); break;
959 case 0x10: handle_101110(regs); break;
960 case 0x11: handle_101111(regs); break;
961 case 0x12: handle_101112(regs); break;
962 case 0x14: handle_101114(regs); break;
963 case 0x30: handle_101130(regs); break;
964 default: handle_1011XX(regs); break;
970 handle_101210(struct bregs *regs)
972 u16 crtc_addr = GET_BDA(crtc_address);
973 if (crtc_addr == VGAREG_MDA_CRTC_ADDRESS)
977 regs->cx = GET_BDA(video_switches) & 0x0f;
981 handle_101230(struct bregs *regs)
983 u8 mctl = GET_BDA(modeset_ctl);
984 u8 vswt = GET_BDA(video_switches);
988 mctl = (mctl & ~0x10) | 0x80;
989 vswt = (vswt & ~0x0f) | 0x08;
994 vswt = (vswt & ~0x0f) | 0x09;
998 mctl = (mctl & ~0x80) | 0x10;
999 vswt = (vswt & ~0x0f) | 0x09;
1002 dprintf(1, "Select vert res (%02x) was discarded\n", regs->al);
1005 SET_BDA(modeset_ctl, mctl);
1006 SET_BDA(video_switches, vswt);
1011 handle_101231(struct bregs *regs)
1013 u8 v = (regs->al & 0x01) << 3;
1014 u8 mctl = GET_BDA(video_ctl) & ~0x08;
1015 SET_BDA(video_ctl, mctl | v);
1020 handle_101232(struct bregs *regs)
1022 vgahw_enable_video_addressing(regs->al);
1027 handle_101233(struct bregs *regs)
1029 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1030 u8 v2 = GET_BDA(modeset_ctl) & ~0x02;
1031 SET_BDA(modeset_ctl, v | v2);
1036 handle_101234(struct bregs *regs)
1038 u8 v = (regs->al & 0x01) ^ 0x01;
1039 u8 v2 = GET_BDA(modeset_ctl) & ~0x01;
1040 SET_BDA(modeset_ctl, v | v2);
1045 handle_101235(struct bregs *regs)
1052 handle_101236(struct bregs *regs)
1059 handle_1012XX(struct bregs *regs)
1065 handle_1012(struct bregs *regs)
1068 case 0x10: handle_101210(regs); break;
1069 case 0x30: handle_101230(regs); break;
1070 case 0x31: handle_101231(regs); break;
1071 case 0x32: handle_101232(regs); break;
1072 case 0x33: handle_101233(regs); break;
1073 case 0x34: handle_101234(regs); break;
1074 case 0x35: handle_101235(regs); break;
1075 case 0x36: handle_101236(regs); break;
1076 default: handle_1012XX(regs); break;
1079 // XXX - cirrus has 1280, 1281, 1282, 1285, 129a, 12a0, 12a1, 12a2, 12ae
1084 handle_1013(struct bregs *regs)
1087 biosfn_write_string(regs->al, regs->bh, regs->bl, regs->cx
1088 , regs->dh, regs->dl, regs->es, (void*)(regs->bp + 0));
1093 handle_101a00(struct bregs *regs)
1095 regs->bx = GET_BDA(dcc_index);
1100 handle_101a01(struct bregs *regs)
1102 SET_BDA(dcc_index, regs->bl);
1103 dprintf(1, "Alternate Display code (%02x) was discarded\n", regs->bh);
1108 handle_101aXX(struct bregs *regs)
1114 handle_101a(struct bregs *regs)
1117 case 0x00: handle_101a00(regs); break;
1118 case 0x01: handle_101a01(regs); break;
1119 default: handle_101aXX(regs); break;
1125 u16 static_functionality_off;
1126 u16 static_functionality_seg;
1146 handle_101b(struct bregs *regs)
1149 struct funcInfo *info = (void*)(regs->di+0);
1150 memset_far(seg, info, 0, sizeof(*info));
1151 // Address of static functionality table
1152 SET_FARVAR(seg, info->static_functionality_off, (u32)static_functionality);
1153 SET_FARVAR(seg, info->static_functionality_seg, get_global_seg());
1155 // Hard coded copy from BIOS area. Should it be cleaner ?
1156 memcpy_far(seg, info->bda_0x49, SEG_BDA, (void*)0x49, 30);
1157 memcpy_far(seg, info->bda_0x84, SEG_BDA, (void*)0x84, 3);
1159 SET_FARVAR(seg, info->dcc_index, GET_BDA(dcc_index));
1160 SET_FARVAR(seg, info->colors, 16);
1161 SET_FARVAR(seg, info->pages, 8);
1162 SET_FARVAR(seg, info->scan_lines, 2);
1163 SET_FARVAR(seg, info->video_mem, 3);
1169 handle_101c00(struct bregs *regs)
1171 u16 flags = regs->cx;
1174 size += sizeof(struct saveVideoHardware);
1176 size += sizeof(struct saveBDAstate);
1178 size += sizeof(struct saveDACcolors);
1184 handle_101c01(struct bregs *regs)
1186 u16 flags = regs->cx;
1188 void *data = (void*)(regs->bx+0);
1190 vgahw_save_state(seg, data);
1191 data += sizeof(struct saveVideoHardware);
1194 biosfn_save_bda_state(seg, data);
1195 data += sizeof(struct saveBDAstate);
1198 vgahw_save_dac_state(seg, data);
1203 handle_101c02(struct bregs *regs)
1205 u16 flags = regs->cx;
1207 void *data = (void*)(regs->bx+0);
1209 vgahw_restore_state(seg, data);
1210 data += sizeof(struct saveVideoHardware);
1213 biosfn_restore_bda_state(seg, data);
1214 data += sizeof(struct saveBDAstate);
1217 vgahw_restore_dac_state(seg, data);
1222 handle_101cXX(struct bregs *regs)
1228 handle_101c(struct bregs *regs)
1231 case 0x00: handle_101c00(regs); break;
1232 case 0x01: handle_101c01(regs); break;
1233 case 0x02: handle_101c02(regs); break;
1234 default: handle_101cXX(regs); break;
1240 handle_104f00(struct bregs *regs)
1242 // XXX - vbe_biosfn_return_controller_information(&AX,ES,DI);
1243 // XXX - OR cirrus_vesa_00h
1247 handle_104f01(struct bregs *regs)
1249 // XXX - vbe_biosfn_return_mode_information(&AX,CX,ES,DI);
1250 // XXX - OR cirrus_vesa_01h
1254 handle_104f02(struct bregs *regs)
1256 // XXX - vbe_biosfn_set_mode(&AX,BX,ES,DI);
1257 // XXX - OR cirrus_vesa_02h
1261 handle_104f03(struct bregs *regs)
1263 // XXX - vbe_biosfn_return_current_mode
1264 // XXX - OR cirrus_vesa_03h
1268 handle_104f04(struct bregs *regs)
1270 // XXX - vbe_biosfn_save_restore_state(&AX, CX, DX, ES, &BX);
1274 handle_104f05(struct bregs *regs)
1276 // XXX - vbe_biosfn_display_window_control
1277 // XXX - OR cirrus_vesa_05h
1281 handle_104f06(struct bregs *regs)
1283 // XXX - vbe_biosfn_set_get_logical_scan_line_length
1284 // XXX - OR cirrus_vesa_06h
1288 handle_104f07(struct bregs *regs)
1290 // XXX - vbe_biosfn_set_get_display_start
1291 // XXX - OR cirrus_vesa_07h
1295 handle_104f08(struct bregs *regs)
1297 // XXX - vbe_biosfn_set_get_dac_palette_format
1301 handle_104f0a(struct bregs *regs)
1303 // XXX - vbe_biosfn_return_protected_mode_interface
1307 handle_104fXX(struct bregs *regs)
1314 handle_104f(struct bregs *regs)
1316 if (! CONFIG_VBE || !vbe_has_vbe_display()) {
1317 handle_104fXX(regs);
1322 case 0x00: handle_104f00(regs); break;
1323 case 0x01: handle_104f01(regs); break;
1324 case 0x02: handle_104f02(regs); break;
1325 case 0x03: handle_104f03(regs); break;
1326 case 0x04: handle_104f04(regs); break;
1327 case 0x05: handle_104f05(regs); break;
1328 case 0x06: handle_104f06(regs); break;
1329 case 0x07: handle_104f07(regs); break;
1330 case 0x08: handle_104f08(regs); break;
1331 case 0x0a: handle_104f0a(regs); break;
1332 default: handle_104fXX(regs); break;
1338 handle_10XX(struct bregs *regs)
1343 // INT 10h Video Support Service Entry Point
1345 handle_10(struct bregs *regs)
1347 debug_enter(regs, DEBUG_VGA_10);
1349 case 0x00: handle_1000(regs); break;
1350 case 0x01: handle_1001(regs); break;
1351 case 0x02: handle_1002(regs); break;
1352 case 0x03: handle_1003(regs); break;
1353 case 0x04: handle_1004(regs); break;
1354 case 0x05: handle_1005(regs); break;
1355 case 0x06: handle_1006(regs); break;
1356 case 0x07: handle_1007(regs); break;
1357 case 0x08: handle_1008(regs); break;
1358 case 0x09: handle_1009(regs); break;
1359 case 0x0a: handle_100a(regs); break;
1360 case 0x0b: handle_100b(regs); break;
1361 case 0x0c: handle_100c(regs); break;
1362 case 0x0d: handle_100d(regs); break;
1363 case 0x0e: handle_100e(regs); break;
1364 case 0x0f: handle_100f(regs); break;
1365 case 0x10: handle_1010(regs); break;
1366 case 0x11: handle_1011(regs); break;
1367 case 0x12: handle_1012(regs); break;
1368 case 0x13: handle_1013(regs); break;
1369 case 0x1a: handle_101a(regs); break;
1370 case 0x1b: handle_101b(regs); break;
1371 case 0x1c: handle_101c(regs); break;
1372 case 0x4f: handle_104f(regs); break;
1373 default: handle_10XX(regs); break;
1378 /****************************************************************
1380 ****************************************************************/
1385 // init detected hardware BIOS Area
1386 // set 80x25 color (not clear from RBIL but usual)
1387 u16 eqf = GET_BDA(equipment_list_flags);
1388 SET_BDA(equipment_list_flags, (eqf & 0xffcf) | 0x20);
1390 // Just for the first int10 find its children
1392 // the default char height
1393 SET_BDA(char_height, 0x10);
1396 SET_BDA(video_ctl, 0x60);
1398 // Set the basic screen we have
1399 SET_BDA(video_switches, 0xf9);
1401 // Set the basic modeset options
1402 SET_BDA(modeset_ctl, 0x51);
1404 // Set the default MSR
1405 SET_BDA(video_msr, 0x09);
1409 vga_post(struct bregs *regs)
1411 debug_enter(regs, DEBUG_VGA_POST);
1420 extern void entry_10(void);
1421 SET_IVT(0x10, get_global_seg(), (u32)entry_10);
1426 // XXX - clear screen and display info
1429 SET_VGA(video_save_pointer_table[0], (u32)video_param_table);
1430 SET_VGA(video_save_pointer_table[1], get_global_seg());
1433 extern u8 _rom_header_size, _rom_header_checksum;
1434 SET_VGA(_rom_header_checksum, 0);
1435 u8 sum = -checksum_far(get_global_seg(), 0, _rom_header_size * 512);
1436 SET_VGA(_rom_header_checksum, sum);