1 // VGA bios implementation
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
10 // * define structs for save/restore state
11 // * review correctness of converted asm by comparing with RBIL
12 // * refactor redundant code into sub-functions
13 // * See if there is a method to the in/out stuff that can be encapsulated.
14 // * remove "biosfn" prefixes
15 // * verify all funcs static
17 // * convert vbe/clext code
19 // * extract hw code from bios interfaces
21 #include "bregs.h" // struct bregs
22 #include "biosvar.h" // GET_BDA
23 #include "util.h" // memset
24 #include "vgatables.h" // find_vga_entry
28 #define CONFIG_CIRRUS 0
31 #define DEBUG_VGA_POST 1
32 #define DEBUG_VGA_10 3
34 #define SET_VGA(var, val) SET_FARVAR(get_global_seg(), (var), (val))
37 // ===================================================================
41 // ===================================================================
43 // -------------------------------------------------------------------
45 call16_vgaint(u32 eax, u32 ebx)
57 // ===================================================================
61 // ===================================================================
63 // -------------------------------------------------------------------
65 biosfn_perform_gray_scale_summing(u16 start, u16 count)
67 inb(VGAREG_ACTL_RESET);
68 outb(0x00, VGAREG_ACTL_ADDRESS);
71 for (i = start; i < start+count; i++) {
72 // set read address and switch to read mode
73 outb(i, VGAREG_DAC_READ_ADDRESS);
74 // get 6-bit wide RGB data values
75 u8 r = inb(VGAREG_DAC_DATA);
76 u8 g = inb(VGAREG_DAC_DATA);
77 u8 b = inb(VGAREG_DAC_DATA);
79 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
80 u16 intensity = ((77 * r + 151 * g + 28 * b) + 0x80) >> 8;
85 // set write address and switch to write mode
86 outb(i, VGAREG_DAC_WRITE_ADDRESS);
87 // write new intensity value
88 outb(intensity & 0xff, VGAREG_DAC_DATA);
89 outb(intensity & 0xff, VGAREG_DAC_DATA);
90 outb(intensity & 0xff, VGAREG_DAC_DATA);
92 inb(VGAREG_ACTL_RESET);
93 outb(0x20, VGAREG_ACTL_ADDRESS);
96 // -------------------------------------------------------------------
98 biosfn_set_cursor_shape(u8 CH, u8 CL)
103 u16 curs = (CH << 8) + CL;
104 SET_BDA(cursor_type, curs);
106 u8 modeset_ctl = GET_BDA(modeset_ctl);
107 u16 cheight = GET_BDA(char_height);
108 if ((modeset_ctl & 0x01) && (cheight > 8) && (CL < 8) && (CH < 0x20)) {
110 CH = ((CH + 1) * cheight / 8) - 1;
112 CH = ((CL + 1) * cheight / 8) - 2;
113 CL = ((CL + 1) * cheight / 8) - 1;
115 // CTRC regs 0x0a and 0x0b
116 u16 crtc_addr = GET_BDA(crtc_address);
117 outb(0x0a, crtc_addr);
118 outb(CH, crtc_addr + 1);
119 outb(0x0b, crtc_addr);
120 outb(CL, crtc_addr + 1);
124 biosfn_get_cursor_shape(u8 page)
128 // FIXME should handle VGA 14/16 lines
129 return GET_BDA(cursor_type);
132 // -------------------------------------------------------------------
134 biosfn_set_cursor_pos(u8 page, u16 cursor)
136 // Should not happen...
141 SET_BDA(cursor_pos[page], cursor);
143 // Set the hardware cursor
144 u8 current = GET_BDA(video_page);
148 // Get the dimensions
149 u16 nbcols = GET_BDA(video_cols);
150 u16 nbrows = GET_BDA(video_rows) + 1;
152 u8 xcurs = cursor & 0x00ff;
153 u8 ycurs = (cursor & 0xff00) >> 8;
155 // Calculate the address knowing nbcols nbrows and page num
156 u16 address = SCREEN_IO_START(nbcols, nbrows, page) + xcurs + ycurs * nbcols;
158 // CRTC regs 0x0e and 0x0f
159 u16 crtc_addr = GET_BDA(crtc_address);
160 outb(0x0e, crtc_addr);
161 outb((address & 0xff00) >> 8, crtc_addr + 1);
162 outb(0x0f, crtc_addr);
163 outb(address & 0x00ff, crtc_addr + 1);
167 biosfn_get_cursor_pos(u8 page)
171 // FIXME should handle VGA 14/16 lines
172 return GET_BDA(cursor_pos[page]);
175 // -------------------------------------------------------------------
177 biosfn_set_active_page(u8 page)
183 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
187 // Get pos curs pos for the right page
188 u16 cursor = biosfn_get_cursor_pos(page);
191 if (GET_GLOBAL(vmode_g->class) == TEXT) {
192 // Get the dimensions
193 u16 nbcols = GET_BDA(video_cols);
194 u16 nbrows = GET_BDA(video_rows) + 1;
196 // Calculate the address knowing nbcols nbrows and page num
197 address = SCREEN_MEM_START(nbcols, nbrows, page);
198 SET_BDA(video_pagestart, address);
201 address = SCREEN_IO_START(nbcols, nbrows, page);
203 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
204 address = page * GET_GLOBAL(vparam_g->slength);
207 // CRTC regs 0x0c and 0x0d
208 u16 crtc_addr = GET_BDA(crtc_address);
209 outb(0x0c, crtc_addr);
210 outb((address & 0xff00) >> 8, crtc_addr + 1);
211 outb(0x0d, crtc_addr);
212 outb(address & 0x00ff, crtc_addr + 1);
214 // And change the BIOS page
215 SET_BDA(video_page, page);
217 dprintf(1, "Set active page %02x address %04x\n", page, address);
219 // Display the cursor, now the page is active
220 biosfn_set_cursor_pos(page, cursor);
224 biosfn_set_video_mode(u8 mode)
225 { // mode: Bit 7 is 1 if no clear screen
227 cirrus_set_video_mode(mode);
230 if (vbe_has_vbe_display())
231 dispi_set_enable(VBE_DISPI_DISABLED);
234 u8 noclearmem = mode & 0x80;
237 // find the entry in the video modes
238 struct vgamode_s *vmode_g = find_vga_entry(mode);
239 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
243 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
244 u16 twidth = GET_GLOBAL(vparam_g->twidth);
245 u16 theightm1 = GET_GLOBAL(vparam_g->theightm1);
246 u16 cheight = GET_GLOBAL(vparam_g->cheight);
248 // Read the bios mode set control
249 u8 modeset_ctl = GET_BDA(modeset_ctl);
251 // Then we know the number of lines
254 // if palette loading (bit 3 of modeset ctl = 0)
255 if ((modeset_ctl & 0x08) == 0) { // Set the PEL mask
256 outb(GET_GLOBAL(vmode_g->pelmask), VGAREG_PEL_MASK);
258 // Set the whole dac always, from 0
259 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
261 // From which palette
262 u8 *palette_g = GET_GLOBAL(vmode_g->dac);
263 u16 palsize = GET_GLOBAL(vmode_g->dacsize) / 3;
264 // Always 256*3 values
266 for (i = 0; i < 0x0100; i++) {
268 outb(GET_GLOBAL(palette_g[(i * 3) + 0]), VGAREG_DAC_DATA);
269 outb(GET_GLOBAL(palette_g[(i * 3) + 1]), VGAREG_DAC_DATA);
270 outb(GET_GLOBAL(palette_g[(i * 3) + 2]), VGAREG_DAC_DATA);
272 outb(0, VGAREG_DAC_DATA);
273 outb(0, VGAREG_DAC_DATA);
274 outb(0, VGAREG_DAC_DATA);
277 if ((modeset_ctl & 0x02) == 0x02)
278 biosfn_perform_gray_scale_summing(0x00, 0x100);
280 // Reset Attribute Ctl flip-flop
281 inb(VGAREG_ACTL_RESET);
285 for (i = 0; i <= 0x13; i++) {
286 outb(i, VGAREG_ACTL_ADDRESS);
287 outb(GET_GLOBAL(vparam_g->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
289 outb(0x14, VGAREG_ACTL_ADDRESS);
290 outb(0x00, VGAREG_ACTL_WRITE_DATA);
293 outb(0, VGAREG_SEQU_ADDRESS);
294 outb(0x03, VGAREG_SEQU_DATA);
295 for (i = 1; i <= 4; i++) {
296 outb(i, VGAREG_SEQU_ADDRESS);
297 outb(GET_GLOBAL(vparam_g->sequ_regs[i - 1]), VGAREG_SEQU_DATA);
301 for (i = 0; i <= 8; i++) {
302 outb(i, VGAREG_GRDC_ADDRESS);
303 outb(GET_GLOBAL(vparam_g->grdc_regs[i]), VGAREG_GRDC_DATA);
306 // Set CRTC address VGA or MDA
307 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
308 if (GET_GLOBAL(vmode_g->memmodel) == MTEXT)
309 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
311 // Disable CRTC write protection
312 outw(0x0011, crtc_addr);
314 for (i = 0; i <= 0x18; i++) {
316 outb(GET_GLOBAL(vparam_g->crtc_regs[i]), crtc_addr + 1);
319 // Set the misc register
320 outb(GET_GLOBAL(vparam_g->miscreg), VGAREG_WRITE_MISC_OUTPUT);
323 outb(0x20, VGAREG_ACTL_ADDRESS);
324 inb(VGAREG_ACTL_RESET);
326 if (noclearmem == 0x00) {
327 if (GET_GLOBAL(vmode_g->class) == TEXT) {
328 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
331 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
333 outb(0x02, VGAREG_SEQU_ADDRESS);
334 u8 mmask = inb(VGAREG_SEQU_DATA);
335 outb(0x0f, VGAREG_SEQU_DATA); // all planes
336 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
337 outb(mmask, VGAREG_SEQU_DATA);
342 SET_BDA(video_mode, mode);
343 SET_BDA(video_cols, twidth);
344 SET_BDA(video_pagesize, GET_GLOBAL(vparam_g->slength));
345 SET_BDA(crtc_address, crtc_addr);
346 SET_BDA(video_rows, theightm1);
347 SET_BDA(char_height, cheight);
348 SET_BDA(video_ctl, (0x60 | noclearmem));
349 SET_BDA(video_switches, 0xF9);
350 SET_BDA(modeset_ctl, GET_BDA(modeset_ctl) & 0x7f);
352 // FIXME We nearly have the good tables. to be reworked
353 SET_BDA(dcc_index, 0x08); // 8 is VGA should be ok for now
354 SET_BDA(video_savetable_ptr, (u32)video_save_pointer_table);
355 SET_BDA(video_savetable_seg, get_global_seg());
358 SET_BDA(video_msr, 0x00); // Unavailable on vanilla vga, but...
359 SET_BDA(video_pal, 0x00); // Unavailable on vanilla vga, but...
362 if (GET_GLOBAL(vmode_g->class) == TEXT)
363 biosfn_set_cursor_shape(0x06, 0x07);
364 // Set cursor pos for page 0..7
365 for (i = 0; i < 8; i++)
366 biosfn_set_cursor_pos(i, 0x0000);
369 biosfn_set_active_page(0x00);
371 // Write the fonts in memory
372 if (GET_GLOBAL(vmode_g->class) == TEXT) {
373 call16_vgaint(0x1104, 0);
374 call16_vgaint(0x1103, 0);
376 // Set the ints 0x1F and 0x43
377 SET_IVT(0x1f, get_global_seg(), (u32)&vgafont8[128 * 8]);
381 SET_IVT(0x43, get_global_seg(), (u32)vgafont8);
384 SET_IVT(0x43, get_global_seg(), (u32)vgafont14);
387 SET_IVT(0x43, get_global_seg(), (u32)vgafont16);
392 // -------------------------------------------------------------------
394 biosfn_write_teletype(u8 car, u8 page, u8 attr, u8 flag)
395 { // flag = WITH_ATTR / NO_ATTR
396 // special case if page is 0xff, use current page
398 page = GET_BDA(video_page);
401 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
405 // Get the cursor pos for the page
406 u16 cursor = biosfn_get_cursor_pos(page);
407 u8 xcurs = cursor & 0x00ff;
408 u8 ycurs = (cursor & 0xff00) >> 8;
410 // Get the dimensions
411 u16 nbrows = GET_BDA(video_rows) + 1;
412 u16 nbcols = GET_BDA(video_cols);
434 biosfn_write_teletype(' ', page, attr, flag);
435 cursor = biosfn_get_cursor_pos(page);
436 xcurs = cursor & 0x00ff;
437 ycurs = (cursor & 0xff00) >> 8;
438 } while (xcurs % 8 == 0);
442 if (flag == WITH_ATTR)
443 biosfn_write_char_attr(car, page, attr, 1);
445 biosfn_write_char_only(car, page, attr, 1);
449 // Do we need to wrap ?
450 if (xcurs == nbcols) {
454 // Do we need to scroll ?
455 if (ycurs == nbrows) {
456 if (GET_GLOBAL(vmode_g->class) == TEXT)
457 biosfn_scroll(0x01, 0x07, 0, 0, nbrows - 1, nbcols - 1, page,
460 biosfn_scroll(0x01, 0x00, 0, 0, nbrows - 1, nbcols - 1, page,
464 // Set the cursor for the page
468 biosfn_set_cursor_pos(page, cursor);
471 // -------------------------------------------------------------------
473 biosfn_get_video_mode(struct bregs *regs)
475 regs->bh = GET_BDA(video_page);
476 regs->al = GET_BDA(video_mode) | (GET_BDA(video_ctl) & 0x80);
477 regs->ah = GET_BDA(video_cols);
481 set_scan_lines(u8 lines)
483 u16 crtc_addr = GET_BDA(crtc_address);
484 outb(0x09, crtc_addr);
485 u8 crtc_r9 = inb(crtc_addr + 1);
486 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
487 outb(crtc_r9, crtc_addr + 1);
489 biosfn_set_cursor_shape(0x06, 0x07);
491 biosfn_set_cursor_shape(lines - 4, lines - 3);
492 SET_BDA(char_height, lines);
493 outb(0x12, crtc_addr);
494 u16 vde = inb(crtc_addr + 1);
495 outb(0x07, crtc_addr);
496 u8 ovl = inb(crtc_addr + 1);
497 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
498 u8 rows = vde / lines;
499 SET_BDA(video_rows, rows - 1);
500 u16 cols = GET_BDA(video_cols);
501 SET_BDA(video_pagesize, rows * cols * 2);
504 // -------------------------------------------------------------------
506 biosfn_get_font_info(u8 BH, u16 *ES, u16 *BP, u16 *CX, u16 *DX)
510 u32 segoff = GET_IVT(0x1f).segoff;
516 u32 segoff = GET_IVT(0x43).segoff;
522 *ES = get_global_seg();
523 *BP = (u32)vgafont14;
526 *ES = get_global_seg();
530 *ES = get_global_seg();
531 *BP = (u32)vgafont8 + 128 * 8;
534 *ES = get_global_seg();
535 *BP = (u32)vgafont14alt;
538 *ES = get_global_seg();
539 *BP = (u32)vgafont16;
542 *ES = get_global_seg();
543 *BP = (u32)vgafont16alt;
546 dprintf(1, "Get font info BH(%02x) was discarded\n", BH);
549 // Set byte/char of on screen font
550 *CX = GET_BDA(char_height) & 0xff;
552 // Set Highest char row
553 *DX = GET_BDA(video_rows);
556 // -------------------------------------------------------------------
558 biosfn_get_ega_info(struct bregs *regs)
560 regs->cx = GET_BDA(video_switches) & 0x0f;
561 regs->ax = GET_BDA(crtc_address);
562 if (regs->ax == VGAREG_MDA_CRTC_ADDRESS)
568 // -------------------------------------------------------------------
570 biosfn_select_vert_res(struct bregs *regs)
572 u8 mctl = GET_BDA(modeset_ctl);
573 u8 vswt = GET_BDA(video_switches);
578 mctl = (mctl & ~0x10) | 0x80;
579 vswt = (vswt & ~0x0f) | 0x08;
584 vswt = (vswt & ~0x0f) | 0x09;
588 mctl = (mctl & ~0x80) | 0x10;
589 vswt = (vswt & ~0x0f) | 0x09;
592 dprintf(1, "Select vert res (%02x) was discarded\n", regs->al);
595 SET_BDA(modeset_ctl, mctl);
596 SET_BDA(video_switches, vswt);
601 biosfn_enable_default_palette_loading(struct bregs *regs)
603 u8 v = (regs->al & 0x01) << 3;
604 u8 mctl = GET_BDA(video_ctl) & ~0x08;
605 SET_BDA(video_ctl, mctl | v);
611 biosfn_enable_grayscale_summing(struct bregs *regs)
613 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
614 u8 v2 = GET_BDA(modeset_ctl) & ~0x02;
615 SET_BDA(modeset_ctl, v | v2);
620 biosfn_enable_cursor_emulation(struct bregs *regs)
622 u8 v = (regs->al & 0x01) ^ 0x01;
623 u8 v2 = GET_BDA(modeset_ctl) & ~0x01;
624 SET_BDA(modeset_ctl, v | v2);
628 // -------------------------------------------------------------------
630 biosfn_write_string(u8 flag, u8 page, u8 attr, u16 count, u8 row, u8 col,
631 u16 seg, u8 *offset_far)
633 // Read curs info for the page
634 u16 oldcurs = biosfn_get_cursor_pos(page);
636 // if row=0xff special case : use current cursor position
638 col = oldcurs & 0x00ff;
639 row = (oldcurs & 0xff00) >> 8;
645 biosfn_set_cursor_pos(page, newcurs);
647 while (count-- != 0) {
648 u8 car = GET_FARVAR(seg, *offset_far);
650 if ((flag & 0x02) != 0) {
651 attr = GET_FARVAR(seg, *offset_far);
655 biosfn_write_teletype(car, page, attr, WITH_ATTR);
659 if ((flag & 0x01) == 0)
660 biosfn_set_cursor_pos(page, oldcurs);
663 // -------------------------------------------------------------------
665 biosfn_read_display_code(struct bregs *regs)
667 regs->bx = GET_BDA(dcc_index);
672 biosfn_set_display_code(struct bregs *regs)
674 SET_BDA(dcc_index, regs->bl);
675 dprintf(1, "Alternate Display code (%02x) was discarded\n", regs->bh);
679 // -------------------------------------------------------------------
681 biosfn_read_state_info(u16 BX, u16 ES, u16 DI)
683 // Address of static functionality table
684 SET_FARVAR(ES, *(u16*)(DI + 0x00), (u32)static_functionality);
685 SET_FARVAR(ES, *(u16*)(DI + 0x02), get_global_seg());
687 // Hard coded copy from BIOS area. Should it be cleaner ?
688 memcpy_far(ES, (void*)(DI + 0x04), SEG_BDA, (void*)0x49, 30);
689 memcpy_far(ES, (void*)(DI + 0x22), SEG_BDA, (void*)0x84, 3);
691 SET_FARVAR(ES, *(u8*)(DI + 0x25), GET_BDA(dcc_index));
692 SET_FARVAR(ES, *(u8*)(DI + 0x26), 0);
693 SET_FARVAR(ES, *(u8*)(DI + 0x27), 16);
694 SET_FARVAR(ES, *(u8*)(DI + 0x28), 0);
695 SET_FARVAR(ES, *(u8*)(DI + 0x29), 8);
696 SET_FARVAR(ES, *(u8*)(DI + 0x2a), 2);
697 SET_FARVAR(ES, *(u8*)(DI + 0x2b), 0);
698 SET_FARVAR(ES, *(u8*)(DI + 0x2c), 0);
699 SET_FARVAR(ES, *(u8*)(DI + 0x31), 3);
700 SET_FARVAR(ES, *(u8*)(DI + 0x32), 0);
702 memset_far(ES, (void*)(DI + 0x33), 0, 13);
705 // -------------------------------------------------------------------
706 // -------------------------------------------------------------------
708 biosfn_read_video_state_size(u16 CX)
714 size += (5 + 8 + 5) * 2 + 6;
716 size += 3 + 256 * 3 + 1;
721 biosfn_save_video_state(u16 CX, u16 ES, u16 BX)
723 u16 crtc_addr = GET_BDA(crtc_address);
725 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_ADDRESS));
727 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr));
729 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_ADDRESS));
731 inb(VGAREG_ACTL_RESET);
732 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
733 SET_FARVAR(ES, *(u8*)(BX+0), ar_index);
735 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_READ_FEATURE_CTL));
739 for (i = 1; i <= 4; i++) {
740 outb(i, VGAREG_SEQU_ADDRESS);
741 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
744 outb(0, VGAREG_SEQU_ADDRESS);
745 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
748 for (i = 0; i <= 0x18; i++) {
750 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr + 1));
754 for (i = 0; i <= 0x13; i++) {
755 inb(VGAREG_ACTL_RESET);
756 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
757 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_ACTL_READ_DATA));
760 inb(VGAREG_ACTL_RESET);
762 for (i = 0; i <= 8; i++) {
763 outb(i, VGAREG_GRDC_ADDRESS);
764 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_DATA));
768 SET_FARVAR(ES, *(u16*)(BX+0), crtc_addr);
771 /* XXX: read plane latches */
772 SET_FARVAR(ES, *(u8*)(BX+0), 0);
774 SET_FARVAR(ES, *(u8*)(BX+0), 0);
776 SET_FARVAR(ES, *(u8*)(BX+0), 0);
778 SET_FARVAR(ES, *(u8*)(BX+0), 0);
782 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_mode));
784 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_cols));
786 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagesize));
788 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(crtc_address));
790 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_rows));
792 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(char_height));
794 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_ctl));
796 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_switches));
798 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(modeset_ctl));
800 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_type));
803 for (i = 0; i < 8; i++) {
804 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_pos[i]));
807 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagestart));
809 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_page));
812 SET_FARVAR(ES, *(u32*)(BX+0), GET_IVT(0x1f).segoff);
814 SET_FARVAR(ES, *(u32*)(BX+0), GET_IVT(0x43).segoff);
818 /* XXX: check this */
819 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_STATE));
820 BX++; /* read/write mode dac */
821 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_WRITE_ADDRESS));
822 BX++; /* pix address */
823 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_PEL_MASK));
825 // Set the whole dac always, from 0
826 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
828 for (i = 0; i < 256 * 3; i++) {
829 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_DATA));
832 SET_FARVAR(ES, *(u8*)(BX+0), 0);
833 BX++; /* color select register */
839 biosfn_restore_video_state(u16 CX, u16 ES, u16 BX)
842 // Reset Attribute Ctl flip-flop
843 inb(VGAREG_ACTL_RESET);
845 u16 crtc_addr = GET_FARVAR(ES, *(u16*)(BX + 0x40));
850 for (i = 1; i <= 4; i++) {
851 outb(i, VGAREG_SEQU_ADDRESS);
852 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
855 outb(0, VGAREG_SEQU_ADDRESS);
856 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
859 // Disable CRTC write protection
860 outw(0x0011, crtc_addr);
862 for (i = 0; i <= 0x18; i++) {
865 outb(GET_FARVAR(ES, *(u8*)(BX+0)), crtc_addr + 1);
869 // select crtc base address
870 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
871 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
873 outb(v, VGAREG_WRITE_MISC_OUTPUT);
875 // enable write protection if needed
876 outb(0x11, crtc_addr);
877 outb(GET_FARVAR(ES, *(u8*)(BX - 0x18 + 0x11)), crtc_addr + 1);
880 u16 ar_index = GET_FARVAR(ES, *(u8*)(addr1 + 0x03));
881 inb(VGAREG_ACTL_RESET);
882 for (i = 0; i <= 0x13; i++) {
883 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
884 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_ACTL_WRITE_DATA);
887 outb(ar_index, VGAREG_ACTL_ADDRESS);
888 inb(VGAREG_ACTL_RESET);
890 for (i = 0; i <= 8; i++) {
891 outb(i, VGAREG_GRDC_ADDRESS);
892 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_GRDC_DATA);
895 BX += 2; /* crtc_addr */
896 BX += 4; /* plane latches */
898 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_SEQU_ADDRESS);
900 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr);
902 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_GRDC_ADDRESS);
905 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr - 0x4 + 0xa);
909 SET_BDA(video_mode, GET_FARVAR(ES, *(u8*)(BX+0)));
911 SET_BDA(video_cols, GET_FARVAR(ES, *(u16*)(BX+0)));
913 SET_BDA(video_pagesize, GET_FARVAR(ES, *(u16*)(BX+0)));
915 SET_BDA(crtc_address, GET_FARVAR(ES, *(u16*)(BX+0)));
917 SET_BDA(video_rows, GET_FARVAR(ES, *(u8*)(BX+0)));
919 SET_BDA(char_height, GET_FARVAR(ES, *(u16*)(BX+0)));
921 SET_BDA(video_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
923 SET_BDA(video_switches, GET_FARVAR(ES, *(u8*)(BX+0)));
925 SET_BDA(modeset_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
927 SET_BDA(cursor_type, GET_FARVAR(ES, *(u16*)(BX+0)));
930 for (i = 0; i < 8; i++) {
931 SET_BDA(cursor_pos[i], GET_FARVAR(ES, *(u16*)(BX+0)));
934 SET_BDA(video_pagestart, GET_FARVAR(ES, *(u16*)(BX+0)));
936 SET_BDA(video_page, GET_FARVAR(ES, *(u8*)(BX+0)));
939 SET_IVT(0x1f, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
941 SET_IVT(0x43, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
946 u16 v = GET_FARVAR(ES, *(u8*)(BX+0));
948 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_PEL_MASK);
950 // Set the whole dac always, from 0
951 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
953 for (i = 0; i < 256 * 3; i++) {
954 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_DAC_DATA);
958 outb(v, VGAREG_DAC_WRITE_ADDRESS);
964 /****************************************************************
966 ****************************************************************/
969 handle_1000(struct bregs *regs)
972 biosfn_set_video_mode(regs->al);
973 switch(regs->al & 0x7F) {
992 handle_1001(struct bregs *regs)
994 biosfn_set_cursor_shape(regs->ch, regs->cl);
998 handle_1002(struct bregs *regs)
1000 biosfn_set_cursor_pos(regs->bh, regs->dx);
1004 handle_1003(struct bregs *regs)
1006 regs->cx = biosfn_get_cursor_shape(regs->bh);
1007 regs->dx = biosfn_get_cursor_pos(regs->bh);
1010 // Read light pen pos (unimplemented)
1012 handle_1004(struct bregs *regs)
1015 regs->ax = regs->bx = regs->cx = regs->dx = 0;
1019 handle_1005(struct bregs *regs)
1021 biosfn_set_active_page(regs->al);
1025 handle_1006(struct bregs *regs)
1027 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
1032 handle_1007(struct bregs *regs)
1034 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
1035 , 0xFF, SCROLL_DOWN);
1039 handle_1008(struct bregs *regs)
1042 biosfn_read_char_attr(regs->bh, ®s->ax);
1046 handle_1009(struct bregs *regs)
1049 biosfn_write_char_attr(regs->al, regs->bh, regs->bl, regs->cx);
1053 handle_100a(struct bregs *regs)
1056 biosfn_write_char_only(regs->al, regs->bh, regs->bl, regs->cx);
1061 handle_100b00(struct bregs *regs)
1063 vgahw_set_border_color(regs->bl);
1067 handle_100b01(struct bregs *regs)
1069 vgahw_set_palette(regs->bl);
1073 handle_100bXX(struct bregs *regs)
1079 handle_100b(struct bregs *regs)
1082 case 0x00: handle_100b00(regs); break;
1083 case 0x01: handle_100b01(regs); break;
1084 default: handle_100bXX(regs); break;
1090 handle_100c(struct bregs *regs)
1093 biosfn_write_pixel(regs->bh, regs->al, regs->cx, regs->dx);
1097 handle_100d(struct bregs *regs)
1100 biosfn_read_pixel(regs->bh, regs->cx, regs->dx, ®s->ax);
1104 handle_100e(struct bregs *regs)
1106 // Ralf Brown Interrupt list is WRONG on bh(page)
1107 // We do output only on the current page !
1108 biosfn_write_teletype(regs->al, 0xff, regs->bl, NO_ATTR);
1112 handle_100f(struct bregs *regs)
1115 biosfn_get_video_mode(regs);
1120 handle_101000(struct bregs *regs)
1122 if (regs->bl > 0x14)
1124 vgahw_set_single_palette_reg(regs->bl, regs->bh);
1128 handle_101001(struct bregs *regs)
1130 vgahw_set_overscan_border_color(regs->bh);
1134 handle_101002(struct bregs *regs)
1136 vgahw_set_all_palette_reg(regs->es, (u8*)(regs->dx + 0));
1140 handle_101003(struct bregs *regs)
1142 vgahw_toggle_intensity(regs->bl);
1146 handle_101007(struct bregs *regs)
1148 if (regs->bl > 0x14)
1150 regs->bh = vgahw_get_single_palette_reg(regs->bl);
1154 handle_101008(struct bregs *regs)
1156 regs->bh = vgahw_get_overscan_border_color(regs);
1160 handle_101009(struct bregs *regs)
1162 vgahw_get_all_palette_reg(regs->es, (u8*)(regs->dx + 0));
1166 handle_101010(struct bregs *regs)
1168 u8 rgb[3] = {regs->dh, regs->ch, regs->cl};
1169 vgahw_set_dac_regs(GET_SEG(SS), rgb, regs->bx, 1);
1173 handle_101012(struct bregs *regs)
1175 vgahw_set_dac_regs(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx);
1179 handle_101013(struct bregs *regs)
1181 vgahw_select_video_dac_color_page(regs->bl, regs->bh);
1185 handle_101015(struct bregs *regs)
1188 vgahw_get_dac_regs(GET_SEG(SS), rgb, regs->bx, 1);
1195 handle_101017(struct bregs *regs)
1197 vgahw_get_dac_regs(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx);
1201 handle_101018(struct bregs *regs)
1203 vgahw_set_pel_mask(regs->bl);
1207 handle_101019(struct bregs *regs)
1209 regs->bl = vgahw_get_pel_mask();
1213 handle_10101a(struct bregs *regs)
1215 vgahw_read_video_dac_state(®s->bl, ®s->bh);
1219 handle_10101b(struct bregs *regs)
1221 biosfn_perform_gray_scale_summing(regs->bx, regs->cx);
1225 handle_1010XX(struct bregs *regs)
1231 handle_1010(struct bregs *regs)
1234 case 0x00: handle_101000(regs); break;
1235 case 0x01: handle_101001(regs); break;
1236 case 0x02: handle_101002(regs); break;
1237 case 0x03: handle_101003(regs); break;
1238 case 0x07: handle_101007(regs); break;
1239 case 0x08: handle_101008(regs); break;
1240 case 0x09: handle_101009(regs); break;
1241 case 0x10: handle_101010(regs); break;
1242 case 0x12: handle_101012(regs); break;
1243 case 0x13: handle_101013(regs); break;
1244 case 0x15: handle_101015(regs); break;
1245 case 0x17: handle_101017(regs); break;
1246 case 0x18: handle_101018(regs); break;
1247 case 0x19: handle_101019(regs); break;
1248 case 0x1a: handle_10101a(regs); break;
1249 case 0x1b: handle_10101b(regs); break;
1250 default: handle_1010XX(regs); break;
1256 handle_101100(struct bregs *regs)
1258 biosfn_load_text_user_pat(regs->es, regs->bp
1259 , regs->cx, regs->dx, regs->bl, regs->bh);
1263 handle_101101(struct bregs *regs)
1265 biosfn_load_text_8_14_pat(regs->bl);
1269 handle_101102(struct bregs *regs)
1271 biosfn_load_text_8_8_pat(regs->bl);
1275 handle_101103(struct bregs *regs)
1277 vgahw_set_text_block_specifier(regs->bl);
1281 handle_101104(struct bregs *regs)
1283 biosfn_load_text_8_16_pat(regs->bl);
1287 handle_101110(struct bregs *regs)
1289 biosfn_load_text_user_pat(regs->es, regs->bp
1290 , regs->cx, regs->dx, regs->bl, regs->bh);
1291 set_scan_lines(regs->bh);
1295 handle_101111(struct bregs *regs)
1297 biosfn_load_text_8_14_pat(regs->bl);
1302 handle_101112(struct bregs *regs)
1304 biosfn_load_text_8_8_pat(regs->bl);
1309 handle_101114(struct bregs *regs)
1311 biosfn_load_text_8_16_pat(regs->bl);
1316 handle_101130(struct bregs *regs)
1319 biosfn_get_font_info(regs->bh, ®s->es, ®s->bp
1320 , ®s->cx, ®s->dx);
1324 handle_1011XX(struct bregs *regs)
1330 handle_1011(struct bregs *regs)
1333 case 0x00: handle_101100(regs); break;
1334 case 0x01: handle_101101(regs); break;
1335 case 0x02: handle_101102(regs); break;
1336 case 0x03: handle_101103(regs); break;
1337 case 0x04: handle_101104(regs); break;
1338 case 0x10: handle_101110(regs); break;
1339 case 0x11: handle_101111(regs); break;
1340 case 0x12: handle_101112(regs); break;
1341 case 0x14: handle_101114(regs); break;
1342 case 0x30: handle_101130(regs); break;
1343 default: handle_1011XX(regs); break;
1349 handle_101210(struct bregs *regs)
1352 biosfn_get_ega_info(regs);
1356 handle_101230(struct bregs *regs)
1359 biosfn_select_vert_res(regs);
1363 handle_101231(struct bregs *regs)
1366 biosfn_enable_default_palette_loading(regs);
1370 handle_101232(struct bregs *regs)
1372 vgahw_enable_video_addressing(regs->al);
1377 handle_101233(struct bregs *regs)
1380 biosfn_enable_grayscale_summing(regs);
1384 handle_101234(struct bregs *regs)
1387 biosfn_enable_cursor_emulation(regs);
1391 handle_101235(struct bregs *regs)
1398 handle_101236(struct bregs *regs)
1405 handle_1012XX(struct bregs *regs)
1411 handle_1012(struct bregs *regs)
1414 case 0x10: handle_101210(regs); break;
1415 case 0x30: handle_101230(regs); break;
1416 case 0x31: handle_101231(regs); break;
1417 case 0x32: handle_101232(regs); break;
1418 case 0x33: handle_101233(regs); break;
1419 case 0x34: handle_101234(regs); break;
1420 case 0x35: handle_101235(regs); break;
1421 case 0x36: handle_101236(regs); break;
1422 default: handle_1012XX(regs); break;
1425 // XXX - cirrus has 1280, 1281, 1282, 1285, 129a, 12a0, 12a1, 12a2, 12ae
1430 handle_1013(struct bregs *regs)
1433 biosfn_write_string(regs->al, regs->bh, regs->bl, regs->cx
1434 , regs->dh, regs->dl, regs->es, (void*)(regs->bp + 0));
1439 handle_101a00(struct bregs *regs)
1442 biosfn_read_display_code(regs);
1446 handle_101a01(struct bregs *regs)
1449 biosfn_set_display_code(regs);
1453 handle_101aXX(struct bregs *regs)
1459 handle_101a(struct bregs *regs)
1462 case 0x00: handle_101a00(regs); break;
1463 case 0x01: handle_101a01(regs); break;
1464 default: handle_101aXX(regs); break;
1470 handle_101b(struct bregs *regs)
1473 biosfn_read_state_info(regs->bx, regs->es, regs->di);
1479 handle_101c00(struct bregs *regs)
1482 regs->bx = biosfn_read_video_state_size(regs->cx);
1486 handle_101c01(struct bregs *regs)
1489 biosfn_save_video_state(regs->cx, regs->es, regs->bx);
1493 handle_101c02(struct bregs *regs)
1496 biosfn_restore_video_state(regs->cx, regs->es, regs->bx);
1500 handle_101cXX(struct bregs *regs)
1506 handle_101c(struct bregs *regs)
1509 case 0x00: handle_101c00(regs); break;
1510 case 0x01: handle_101c01(regs); break;
1511 case 0x02: handle_101c02(regs); break;
1512 default: handle_101cXX(regs); break;
1518 handle_104f00(struct bregs *regs)
1520 // XXX - vbe_biosfn_return_controller_information(&AX,ES,DI);
1521 // XXX - OR cirrus_vesa_00h
1525 handle_104f01(struct bregs *regs)
1527 // XXX - vbe_biosfn_return_mode_information(&AX,CX,ES,DI);
1528 // XXX - OR cirrus_vesa_01h
1532 handle_104f02(struct bregs *regs)
1534 // XXX - vbe_biosfn_set_mode(&AX,BX,ES,DI);
1535 // XXX - OR cirrus_vesa_02h
1539 handle_104f03(struct bregs *regs)
1541 // XXX - vbe_biosfn_return_current_mode
1542 // XXX - OR cirrus_vesa_03h
1546 handle_104f04(struct bregs *regs)
1548 // XXX - vbe_biosfn_save_restore_state(&AX, CX, DX, ES, &BX);
1552 handle_104f05(struct bregs *regs)
1554 // XXX - vbe_biosfn_display_window_control
1555 // XXX - OR cirrus_vesa_05h
1559 handle_104f06(struct bregs *regs)
1561 // XXX - vbe_biosfn_set_get_logical_scan_line_length
1562 // XXX - OR cirrus_vesa_06h
1566 handle_104f07(struct bregs *regs)
1568 // XXX - vbe_biosfn_set_get_display_start
1569 // XXX - OR cirrus_vesa_07h
1573 handle_104f08(struct bregs *regs)
1575 // XXX - vbe_biosfn_set_get_dac_palette_format
1579 handle_104f0a(struct bregs *regs)
1581 // XXX - vbe_biosfn_return_protected_mode_interface
1585 handle_104fXX(struct bregs *regs)
1592 handle_104f(struct bregs *regs)
1594 if (! CONFIG_VBE || !vbe_has_vbe_display()) {
1595 handle_104fXX(regs);
1600 case 0x00: handle_104f00(regs); break;
1601 case 0x01: handle_104f01(regs); break;
1602 case 0x02: handle_104f02(regs); break;
1603 case 0x03: handle_104f03(regs); break;
1604 case 0x04: handle_104f04(regs); break;
1605 case 0x05: handle_104f05(regs); break;
1606 case 0x06: handle_104f06(regs); break;
1607 case 0x07: handle_104f07(regs); break;
1608 case 0x08: handle_104f08(regs); break;
1609 case 0x0a: handle_104f0a(regs); break;
1610 default: handle_104fXX(regs); break;
1616 handle_10XX(struct bregs *regs)
1621 // INT 10h Video Support Service Entry Point
1623 handle_10(struct bregs *regs)
1625 debug_enter(regs, DEBUG_VGA_10);
1627 case 0x00: handle_1000(regs); break;
1628 case 0x01: handle_1001(regs); break;
1629 case 0x02: handle_1002(regs); break;
1630 case 0x03: handle_1003(regs); break;
1631 case 0x04: handle_1004(regs); break;
1632 case 0x05: handle_1005(regs); break;
1633 case 0x06: handle_1006(regs); break;
1634 case 0x07: handle_1007(regs); break;
1635 case 0x08: handle_1008(regs); break;
1636 case 0x09: handle_1009(regs); break;
1637 case 0x0a: handle_100a(regs); break;
1638 case 0x0b: handle_100b(regs); break;
1639 case 0x0c: handle_100c(regs); break;
1640 case 0x0d: handle_100d(regs); break;
1641 case 0x0e: handle_100e(regs); break;
1642 case 0x0f: handle_100f(regs); break;
1643 case 0x10: handle_1010(regs); break;
1644 case 0x11: handle_1011(regs); break;
1645 case 0x12: handle_1012(regs); break;
1646 case 0x13: handle_1013(regs); break;
1647 case 0x1a: handle_101a(regs); break;
1648 case 0x1b: handle_101b(regs); break;
1649 case 0x1c: handle_101c(regs); break;
1650 case 0x4f: handle_104f(regs); break;
1651 default: handle_10XX(regs); break;
1656 /****************************************************************
1658 ****************************************************************/
1663 // init detected hardware BIOS Area
1664 // set 80x25 color (not clear from RBIL but usual)
1665 u16 eqf = GET_BDA(equipment_list_flags);
1666 SET_BDA(equipment_list_flags, (eqf & 0xffcf) | 0x20);
1668 // Just for the first int10 find its children
1670 // the default char height
1671 SET_BDA(char_height, 0x10);
1674 SET_BDA(video_ctl, 0x60);
1676 // Set the basic screen we have
1677 SET_BDA(video_switches, 0xf9);
1679 // Set the basic modeset options
1680 SET_BDA(modeset_ctl, 0x51);
1682 // Set the default MSR
1683 SET_BDA(video_msr, 0x09);
1687 vga_post(struct bregs *regs)
1689 debug_enter(regs, DEBUG_VGA_POST);
1698 extern void entry_10(void);
1699 SET_IVT(0x10, get_global_seg(), (u32)entry_10);
1704 // XXX - clear screen and display info
1707 SET_VGA(video_save_pointer_table[0], (u32)video_param_table);
1708 SET_VGA(video_save_pointer_table[1], get_global_seg());
1711 extern u8 _rom_header_size, _rom_header_checksum;
1712 SET_VGA(_rom_header_checksum, 0);
1713 u8 sum = -checksum_far(get_global_seg(), 0, _rom_header_size * 512);
1714 SET_VGA(_rom_header_checksum, sum);